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软件版本:Anlogic -TD5.6.1-64bit 操作系统:WIN10 64bit 硬件平台:适用安路(Anlogic)FPGA 1概述本文简述了图像均值滤波的算法,讲解如何进行Verilog的算法实现,并进行上板实验。 2算法原理简介均值滤波也称为线性滤波,其采用的主要方法为邻域平均法。线性滤波的基本原理是用均值代替原图像中的各个像素值,即对待处理的当前像素点(x,y),选择一个模板,该模板由其近邻的若干像素组成,求模板中所有像素的均值,再把该均值赋予当前像素点(x,y),作为处理后图像在该点上的灰度g(x,y),即 m为该模板中包含当前像素在内的像素总个数。图像处理的模板在上一讲介绍过,3x3或5x5的模板都可以用于均值滤波。 3算法仿真
3.1Matlab算法仿真
3.1.1Matlab算法代码分析源代码如下:
- clear;clear all;clc;
-
- image_in = imread('lena_1280x720.jpg');
- % [row,col,n] = size(image_in);
-
- image_gray = rgb2gray(image_in);
- [row,col] = size(image_gray);
-
- image_gray = im2double(image_gray);
- average_image = zeros(row,col);
- for i = 2:1:row-1
- for j = 2:1:col-1
- average_image(i,j) = (...
- image_gray(i-1,j-1)+image_gray(i-1,j)+image_gray(i-1,j+1)+...
- image_gray(i,j-1) +image_gray(i,j) +image_gray(i,j+1) +...
- image_gray(i+1,j-1)+image_gray(i+1,j)+image_gray(i+1,j+1))/9;
- end
- end
-
- image_gray1 = imnoise(image_gray,'salt & pepper',0.05);
- image_gray1 = im2double(image_gray1);
- average_image1 = zeros(row,col);
- for i = 2:1:row-1
- for j = 2:1:col-1
- average_image1(i,j) = (...
- image_gray1(i-1,j-1)+image_gray1(i-1,j)+image_gray1(i-1,j+1)+...
- image_gray1(i,j-1) +image_gray1(i,j) +image_gray1(i,j+1) +...
- image_gray1(i+1,j-1)+image_gray1(i+1,j)+image_gray1(i+1,j+1))/9;
- end
- end
-
- image_gray2 = imnoise(image_gray,'gaussian',0.05);
- image_gray2 = im2double(image_gray2);
- average_image2 = zeros(row,col);
- for i = 2:1:row-1
- for j = 2:1:col-1
- average_image2(i,j) = (...
- image_gray2(i-1,j-1)+image_gray2(i-1,j)+image_gray2(i-1,j+1)+...
- image_gray2(i,j-1) +image_gray2(i,j) +image_gray2(i,j+1) +...
- image_gray2(i+1,j-1)+image_gray2(i+1,j)+image_gray2(i+1,j+1))/9;
- end
- end
-
- figure
- subplot(321);
- imshow(image_gray ), title('the original gray image');
- subplot(322);
- imshow(average_image), title('the average image');
- subplot(323);
- imshow(image_gray1), title('the salt & pepper image');
- subplot(324);
- imshow(average_image1), title('the average1 image');
- subplot(325);
- imshow(image_gray2), title('the gaussian image');
- subplot(326);
- imshow(average_image2), title('the average2 image');
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3.1.2Matlab实验结果
3.2Verilog算法仿真
3.2.1Modelsim仿真
3.2.1.1仿真执行在件夹Algorithm_simulation下进行算法的仿真,分为sim,src和tb三个子文件夹。在sim文件夹下有win系统的快捷执行文件sim.bat,可以一键进行仿真,src文件下放的是Verilog的核心图像算法及其顶层与输入图像激励,tb文件下放的是测试激励文件及输出图像的保存。 双击执行sim文件夹下sim.bat,自动打开Modelsim仿真,自动添加仿真波形,执行完成后自动保存图像,仿真波形如图所示: 3.2.1.2仿真关键部分代码解析- #
- # Create work library
- #
- vlib work
- #
- # Compile sources
- #
- vlog "../src/*.v"
- vlog "../tb/*.v"
- #
- # Call vsim to invoke simulator
- #
- vsim -voptargs=+acc work.top_tb
- #
- # Add waves
- #
- do wave.do
- #
- # Run simulation
- #
- run -all
- #
- # End
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- reg en;
- reg [12:0] h_syn_cnt = 'd0;
- reg [12:0] v_syn_cnt = 'd0;
- reg [23:0] image [0 : H_ACTIVE*V_ACTIVE-1];
- reg [31:0] image_cnt = 'd0;
-
- //读取txt文件到image数组中
- initial begin
- $readmemh("../matlab_src/image_720_1280_3.txt", image);
- end
-
- // 行扫描计数器
- always@(posedge i_clk)
- begin
- if(h_syn_cnt == H_TOTAL_TIME-1)
- h_syn_cnt <= 0;
- else
- h_syn_cnt <= h_syn_cnt + 1;
- end
-
- // 列扫描计数器
- always@(posedge i_clk)
- begin
- if(h_syn_cnt == H_TOTAL_TIME-1)
- begin
- if(v_syn_cnt == V_TOTAL_TIME-1)
- v_syn_cnt <= 0;
- else
- v_syn_cnt <= v_syn_cnt + 1;
- end
- end
-
- // 行同步控制
- always@(posedge i_clk)
- begin
- if(h_syn_cnt < H_SYNC_TIME)
- o_hsyn <= 0;
- else
- o_hsyn <= 1;
- end
-
- // 场同步控制
- always@(posedge i_clk)
- begin
- if(v_syn_cnt < V_SYNC_TIME)
- o_vsyn <= 0;
- else
- o_vsyn <= 1;
- end
-
- // 坐标使能.
- always@(posedge i_clk)
- begin
- if(v_syn_cnt >= V_SYNC_TIME + V_BACK_PORCH && v_syn_cnt < V_SYNC_TIME + V_BACK_PORCH + V_ACTIVE)
- begin
- if(h_syn_cnt >= H_SYNC_TIME + H_BACK_PORCH && h_syn_cnt < H_SYNC_TIME + H_BACK_PORCH + H_ACTIVE)
- en <= 1;
- else
- en <= 0;
- end
- else
- en <= 0;
- end
-
- always@(posedge i_clk)
- begin
- if(en)
- begin
- o_r <= image[image_cnt][23:16];
- o_g <= image[image_cnt][15:8];
- o_b <= image[image_cnt][7:0];
- image_cnt <= image_cnt + 1;
- end
- else if(image_cnt == H_ACTIVE*V_ACTIVE)
- begin
- o_r <= 8'h00;
- o_g <= 8'h00;
- o_b <= 8'h00;
- image_cnt <= 'd0;
- end
- else
- begin
- o_r <= 8'h00;
- o_g <= 8'h00;
- o_b <= 8'h00;
- image_cnt <= image_cnt;
- end
- end
-
- always@(posedge i_clk)
- begin
-
- // if(image_cnt >= H_ACTIVE*V_ACTIVE)
- // o_en <= 0;
- // else
- o_en <= en;
- end
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- reg clk;
- reg rst_n;
-
- integer image_txt;
-
- reg [31:0] pixel_cnt;
- wire[23:0] data;
- wire de;
-
-
- top u_top
- (
- .i_clk (clk ),
- .i_rst_n (rst_n ),
- .o_gray_data (data ),
- .o_gray_de (de )
- );
-
- always #(1) clk = ~clk;
-
- initial
- begin
- clk = 1;
- rst_n = 0;
- #100
- rst_n = 1;
-
- end
-
- glbl glbl();
-
- initial
- begin
- image_txt = $fopen("../matlab_src/image_720_1280_3_out.txt");
- end
-
- always@(posedge clk or negedge rst_n)
- begin
- if(!rst_n)
- begin
- pixel_cnt <= 0;
- end
- else if(de)
- begin
- pixel_cnt = pixel_cnt + 1;
- $fwrite(image_txt,"%h\n",data);
- end
- end
-
- always@(posedge clk )
- begin
- if(pixel_cnt == 720*1280)
- begin
- $display("*******************************************************************************");
- $display("*** Success:image_720_1280_3_out.txt is output complete! %t", $realtime, "ps***");
- $display("*******************************************************************************");
- $fclose(image_txt);
- $stop;
- end
- end
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3.2.2Modelsim实验结果- clear;clear all;clc;
-
- row = 720;
- col = 1280;
- n = 3;
-
- image_sim_pass = uint8(zeros(row,col,n));
- fid = fopen('image_720_1280_3_out.txt','r');
- for x = 1:row
- for y = 1:col
- RGB = fscanf(fid,'%s',1);
- image_sim_pass(x,y,1) = uint8(hex2dec(RGB(1:2)));
- image_sim_pass(x,y,2) = uint8(hex2dec(RGB(3:4)));
- image_sim_pass(x,y,3) = uint8(hex2dec(RGB(5:6)));
- end
- end
- fclose(fid);
-
- image_1 = imread('lena_1280x720.jpg');
-
- subplot(121);
- imshow(image_1), title('The original image');
-
- subplot(122);
- imshow(image_sim_pass),title('After processing images');
-
- imwrite(image_sim_pass,'lena_720x128_sim_pass.jpg');
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4工程实现
4.1Verilog代码分析变量声明 - reg [2:0] i_hsyn_d;
- reg [2:0] i_vsyn_d;
- reg [2:0] i_en_d;
-
- reg [11:0] sum_r;
- reg [11:0] sum_g;
- reg [11:0] sum_b;
-
- reg [7:0] avg_r;
- reg [7:0] avg_g;
- reg [7:0] avg_b;
-
- wire [7:0] r_temp_11;
- wire [7:0] r_temp_12;
- wire [7:0] r_temp_13;
- wire [7:0] r_temp_21;
- wire [7:0] r_temp_22;
- wire [7:0] r_temp_23;
- wire [7:0] r_temp_31;
- wire [7:0] r_temp_32;
- wire [7:0] r_temp_33;
-
- wire [7:0] g_temp_11;
- wire [7:0] g_temp_12;
- wire [7:0] g_temp_13;
- wire [7:0] g_temp_21;
- wire [7:0] g_temp_22;
- wire [7:0] g_temp_23;
- wire [7:0] g_temp_31;
- wire [7:0] g_temp_32;
- wire [7:0] g_temp_33;
-
- wire [7:0] b_temp_11;
- wire [7:0] b_temp_12;
- wire [7:0] b_temp_13;
- wire [7:0] b_temp_21;
- wire [7:0] b_temp_22;
- wire [7:0] b_temp_23;
- wire [7:0] b_temp_31;
- wire [7:0] b_temp_32;
- wire [7:0] b_temp_33;
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输出赋值 - assign o_hs = i_hsyn_d[2];
- assign o_vs = i_vsyn_d[2];
- assign o_en = i_en_d[2] ;
-
- assign o_r = avg_r;
- assign o_g = avg_g;
- assign o_b = avg_b;
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信号同步化处理 - always@(posedge i_clk )
- begin
- i_hsyn_d <= {i_hsyn_d[1:0],i_hsyn};
- i_vsyn_d <= {i_vsyn_d[1:0],i_vsyn};
- i_en_d <= {i_en_d[1:0],i_en};
- end
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调用3x3模板 - image_template u_r_template
- (
- .i_clk (i_clk ),
- .i_rst_n (i_rst_n ),
- .i_en (i_en ),
- .i_data (i_r ),
- .o_en ( ),
- .o_temp_11 (r_temp_11 ),
- .o_temp_12 (r_temp_12 ),
- .o_temp_13 (r_temp_13 ),
- .o_temp_21 (r_temp_21 ),
- .o_temp_22 (r_temp_22 ),
- .o_temp_23 (r_temp_23 ),
- .o_temp_31 (r_temp_31 ),
- .o_temp_32 (r_temp_32 ),
- .o_temp_33 (r_temp_33 )
- );
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调用3x3模板 - image_template u_g_template
- (
- .i_clk (i_clk ),
- .i_rst_n (i_rst_n ),
- .i_en (i_en ),
- .i_data (i_g ),
- .o_en ( ),
- .o_temp_11 (g_temp_11 ),
- .o_temp_12 (g_temp_12 ),
- .o_temp_13 (g_temp_13 ),
- .o_temp_21 (g_temp_21 ),
- .o_temp_22 (g_temp_22 ),
- .o_temp_23 (g_temp_23 ),
- .o_temp_31 (g_temp_31 ),
- .o_temp_32 (g_temp_32 ),
- .o_temp_33 (g_temp_33 )
- );
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调用3x3模板 - image_template u_b_template
- (
- .i_clk (i_clk ),
- .i_rst_n (i_rst_n ),
- .i_en (i_en ),
- .i_data (i_b ),
- .o_en ( ),
- .o_temp_11 (b_temp_11 ),
- .o_temp_12 (b_temp_12 ),
- .o_temp_13 (b_temp_13 ),
- .o_temp_21 (b_temp_21 ),
- .o_temp_22 (b_temp_22 ),
- .o_temp_23 (b_temp_23 ),
- .o_temp_31 (b_temp_31 ),
- .o_temp_32 (b_temp_32 ),
- .o_temp_33 (b_temp_33 )
- );
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执行求和运算 - always@(posedge i_clk or negedge i_rst_n)
- begin
- if(!i_rst_n)
- begin
- sum_r <= 12'd0;
- sum_g <= 12'd0;
- sum_b <= 12'd0;
- end
- else
- begin
- sum_r <= r_temp_11 +
- r_temp_12 +
- r_temp_13 +
- r_temp_21 +
- // r_temp_22 +
- r_temp_23 +
- r_temp_31 +
- r_temp_32 +
- r_temp_33;
- sum_g <= g_temp_11 +
- g_temp_12 +
- g_temp_13 +
- g_temp_21 +
- // g_temp_22 +
- g_temp_23 +
- g_temp_31 +
- g_temp_32 +
- g_temp_33 ;
- sum_b <= b_temp_11 +
- b_temp_12 +
- b_temp_13 +
- b_temp_21 +
- // b_temp_22 +
- b_temp_23 +
- b_temp_31 +
- b_temp_32 +
- b_temp_33 ;
- end
- end
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执行右移动三位运算,等同于除法除去8 - always@(posedge i_clk or negedge i_rst_n)
- begin
- if(!i_rst_n)
- begin
- avg_r <= 8'd0;
- avg_g <= 8'd0;
- avg_b <= 8'd0;
- end
- else
- begin
- avg_r <= sum_r>>3;
- avg_g <= sum_g>>3;
- avg_b <= sum_b>>3;
- end
- end
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4.2工程结构工程结构如图所示: 图像数据通过摄像头采集进来,先缓存在fifo中,然后通过写状态机,将图像数据送进DDR进行缓存,缓存后的图像数据从DDR中取出,通过读状态机送出到fifo中,然后算法处理模块在fifo中取出数据,完成数据处理后送到LCD进行显示输出。 5上板实验点击下载后,可以看到正常的输出如下所示,摄像头的分辨率为640x48
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