FPGA跨时钟检测上升沿简单处理方法

  FPGA跨时钟检测上升沿有很多方法，这里给大家介绍一个非常简单的方法，就是用xilinx带参数宏解决。

This macro synchronizes a pulse in the source clock domain to the destination clock domain. A
pulse of any size in the source clock domain, if initiated correctly, will generate a pulse the size of
a single destination clock period。（不管源端脉宽多宽，都将产生脉冲信号，这个脉冲信号只有一个目的时钟节宽度）
xpm_cdc_pulse是从源信号src_pulse的脉冲里面检测出上升沿，从dest_pulse输出（只维持一个时钟节拍）。

// xpm_cdc_single: Single-bit Synchronizer
// Xilinx Parameterized Macro, version 2019.1
xpm_cdc_single #(
.DEST_SYNC_FF(4), // DECIMAL; range: 2-10
.INIT_SYNC_FF(0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
.SRC_INPUT_REG(1) // DECIMAL; 0=do not register input, 1=register input
)
xpm_cdc_single_inst (
.dest_out(dest_out), // 1-bit output: src_in synchronized to the destination clock domain. This output is
// registered.
.dest_clk(dest_clk), // 1-bit input: Clock signal for the destination clock domain.
.src_clk(src_clk), // 1-bit input: optional; required when SRC_INPUT_REG = 1
.src_in(src_in) // 1-bit input: Input signal to be synchronized to dest_clk domain.
);
// End of xpm_cdc_single_inst instantiation