同步FIFO设计

module fifo_serial(
   input clk,
   input ren,
   input rst,
   input wen,
   input [7:0]data_in,
   output full,
   output empty,
   output [7:0]data_out
);
   reg [9:0]waddr;
   reg [9:0]raddr;
   reg [10:0]count;

   wire wen_wire;
   wire ren_wire;

   always@(posedge clk or negedge rst)
   if(!rst)
      waddr<=1'b0;
   else if(wen==1'b0&&full!=1'b1)
      waddr<=waddr+1;
   else
      waddr<=waddr;

   always@(posedge clk or negedge rst)
   if(!rst)
      raddr<=1'b0;
   else if(wen==1'b0&&empty!=1'b1)
      raddr<=raddr+1;
   else
      raddr<=raddr;

   always@(posedge clk or negedge rst)
   if(!rst)
      count<=11'b0;
      else
      begin
         case({wen,ren})
            2'b00:
                  begin
                        count<=count;
                  end
2'b01:
                  begin
                        if(full==1'b0)
         count<=count+1;
   else
         count<=count;
   end
2'b10:
                  begin
                        if(empty==1'b0)
         count<=count-1;
   else
         count<=count;
                  end
      default:
   begin
                        count<=count;
                  end
      endcase
end
assign empty=(count==1'b0)?1:0;
      assign full=(count==11'h400)?1:0;

      assign wen_wire=(full==1'b1)?1:wen;
      assign ren_wire=(empty==1'b1)?1:ren;
         //例化双口RAM
      dpram1k u1( ..... );
endmodule

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