`timescale 1ns / 1ps

/*******************************MILIANKE*******************************
*Company : MiLianKe Electronic Technology Co., Ltd.
*WebSite:https://www.milianke.com
*TechWeb:https://www.uisrc.com
*tmall-shop:https://milianke.tmall.com
*jd-shop:https://milianke.jd.com
*taobao-shop1: https://milianke.taobao.com
*Create Date: 2021/10/15
*File Name: pcie_top.v
*Description: 
*Declaration:
*The reference demo provided by Milianke is only used for learning. 
*We cannot ensure that the demo itself is free of bugs, so users 
*should be responsible for the technical problems and consequences
*caused by the use of their own products.
*Copyright: Copyright (c) MiLianKe
*All rights reserved.
*Revision: 1.0
*Signal description
*1) _i input
*2) _o output
*3) _n activ low
*4) _dg debug signal 
*5) _r delay or register
*6) _s state mechine
*********************************************************************/

module pcie_top
(
  output [14:0]DDR3_addr,
  output [2:0]DDR3_ba,
  output DDR3_cas_n,
  output [0:0]DDR3_ck_n,
  output [0:0]DDR3_ck_p,
  output [0:0]DDR3_cke,
  output [0:0]DDR3_cs_n,
  output [7:0]DDR3_dm,
  inout [63:0]DDR3_dq,
  inout [7:0]DDR3_dqs_n,
  inout [7:0]DDR3_dqs_p,
  output [0:0]DDR3_odt,
  output DDR3_ras_n,
  output DDR3_reset_n,
  output DDR3_we_n,
  input  sysclk_p,
  input  sysclk_n,
  
  input  [7 :0]pcie_mgt_rxn,
  input  [7 :0]pcie_mgt_rxp,
  output [7 :0]pcie_mgt_txn,
  output [7 :0]pcie_mgt_txp,
  input  [0 :0]pcie_ref_clk_n,
  input  [0 :0]pcie_ref_clk_p,
  input pcie_rst_n
    );

wire sysclk;
IBUFDS CLK_U(.I(sysclk_p),.IB(sysclk_n),.O(sysclk));

wire axi_aclk;
wire user_irq_en_o;
reg  [21:0]timer_cnt;
reg  timer_r1,timer_r2;
reg [1:0]int_p;
reg [3:0]user_irq_req_i;
wire inter = !timer_r2 && timer_r1;

always @(posedge axi_aclk)begin
    if(user_irq_en_o == 1'b0)begin
            timer_cnt <= 22'd0;
    end
    else begin
            timer_cnt <= timer_cnt + 1'b1;
    end
end

always @(posedge axi_aclk)begin
    if(user_irq_en_o == 1'b0)begin
            timer_r1 <= 1'd0;
            timer_r2 <= 1'd0;
    end
    else begin
            timer_r1 <= timer_cnt[20];
            timer_r2 <= timer_r1;
    end
end

always @(posedge axi_aclk)begin
    if(user_irq_en_o == 1'b0)begin
            int_p[1:0]  <= 4'd0;
            user_irq_req_i <= 4'd0;
    end 
    else begin
        if(inter)  int_p <= int_p + 1'b1;
        user_irq_req_i <= 4'd0;
        user_irq_req_i[int_p] <= 1'b1;   
    end
end

pcie_system pcie_system_i(
.DDR3_addr(DDR3_addr),
.DDR3_ba(DDR3_ba),
.DDR3_cas_n(DDR3_cas_n),
.DDR3_ck_n(DDR3_ck_n),
.DDR3_ck_p(DDR3_ck_p),
.DDR3_cke(DDR3_cke),
.DDR3_cs_n(DDR3_cs_n),
.DDR3_dm(DDR3_dm),
.DDR3_dq(DDR3_dq),
.DDR3_dqs_n(DDR3_dqs_n),
.DDR3_dqs_p(DDR3_dqs_p),
.DDR3_odt(DDR3_odt),
.DDR3_ras_n(DDR3_ras_n),
.DDR3_reset_n(DDR3_reset_n),
.DDR3_we_n(DDR3_we_n),
   
.pcie_mgt_rxn(pcie_mgt_rxn),
.pcie_mgt_rxp(pcie_mgt_rxp),
.pcie_mgt_txn(pcie_mgt_txn),
.pcie_mgt_txp(pcie_mgt_txp),
.pcie_ref_clk_n(pcie_ref_clk_n),
.pcie_ref_clk_p(pcie_ref_clk_p),
.pcie_rst_n(pcie_rst_n),
.axi_aclk(axi_aclk),
.user_irq_en_o(user_irq_en_o),
.user_irq_req_i(user_irq_req_i),
.sysclk(sysclk)
);
        
      
endmodule
复制代码

/*******************************MILIANKE*******************************
*Company : MiLianKe Electronic Technology Co., Ltd.
*WebSite:https://www.milianke.com
*TechWeb:https://www.uisrc.com
*tmall-shop:https://milianke.tmall.com
*jd-shop:https://milianke.jd.com
*taobao-shop1: https://milianke.taobao.com
*Create Date : 2022/05/01
*Module Name:uixdmairq
*File Name:uixdmairq.v
*Description :
*The reference demo provided by Milianke is only used for learning.
*We cannot ensure that the demo itself is free of bugs, so users
*should be responsible for the technical problems and consequences
*caused by the use of their own products.
*Copyright: Copyright (c) MiLianKe
*All rights reserved.
*Revision : 1.0
*Signal description
*1) _i input
*2) _o output
*3) _n activ low
*4) _dg debug signal
*5) _r delay or register
*6) _s state mechine
*********************************************************************/
`timescale 1ns / 1ps

module uixdmairq #
(
parameter integer XMDA_REQ_NUM = 8
)
(
// Users to add ports here
input  wire [XMDA_REQ_NUM-1 :0] user_irq_req_i,
//input  wire [XMDA_REQ_NUM-1 :0] xdma_irq_ack_i,
output wire [XMDA_REQ_NUM-1 :0] xdma_irq_req_o,
output wire user_irq_en_o,
input wire  S_AXI_ACLK,
input wire  S_AXI_ARESETN,
input wire [3 : 0] S_AXI_AWADDR,
input wire [2 : 0] S_AXI_AWPROT,
input wire  S_AXI_AWVALID,
output wire  S_AXI_AWREADY,
input wire [31 : 0] S_AXI_WDATA,
input wire [3  : 0] S_AXI_WSTRB,
input wire  S_AXI_WVALID,
output wire  S_AXI_WREADY,
output wire [1 : 0] S_AXI_BRESP,
output wire  S_AXI_BVALID,
input wire  S_AXI_BREADY,
input wire [3 : 0] S_AXI_ARADDR,
input wire [2 : 0] S_AXI_ARPROT,
input wire  S_AXI_ARVALID,
output wire  S_AXI_ARREADY,
output wire [31 : 0] S_AXI_RDATA,
output wire [1  : 0] S_AXI_RRESP,
output wire  S_AXI_RVALID,
input wire  S_AXI_RREADY
);



reg  [XMDA_REQ_NUM -1 :0] user_irq_req;
reg  [XMDA_REQ_NUM -1 :0] user_irq_req_r1;
reg  [XMDA_REQ_NUM -1 :0] user_irq_req_r2;
reg  [XMDA_REQ_NUM -1 :0] user_irq_req_r3;
reg  [XMDA_REQ_NUM -1 :0] xdma_irq_ack_r1;
reg  [XMDA_REQ_NUM -1 :0] xdma_irq_ack_r2;
reg  [XMDA_REQ_NUM -1 :0] xdma_irq_ack_r3;
//reg  [XMDA_REQ_NUM -1 :0] xdma_irq_ack;
reg  [XMDA_REQ_NUM -1 :0] xdma_irq_req;
// AXI4LITE signals
reg [3:0]        axi_awaddr;
reg     axi_awready;
reg     axi_wready;
reg [1 : 0]     axi_bresp;
reg     axi_bvalid;
reg [3:0]       axi_araddr;
reg     axi_arready;
reg [31 : 0]    axi_rdata;
reg [1  : 0]    axi_rresp;
reg     axi_rvalid;

// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C S AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = 2;
localparam integer OPT_MEM_ADDR_BITS = 1;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 4
reg [31:0]  slv_reg0;
reg [31:0]  slv_reg1;
wire     slv_reg_rden;
wire     slv_reg_wren;
reg [31:0]   reg_data_out;
integer  byte_index;
reg  aw_en;

// I/O Connections assignments

assign S_AXI_AWREADY    = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP  = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA  = axi_rdata;
assign S_AXI_RRESP  = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1 'b0 )
begin
axi_awready <= 1 'b0;
aw_en <= 1 'b1;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1 'b1;
aw_en <= 1 'b0;
end
else if (S_AXI_BREADY && axi_bvalid)
begin
aw_en <= 1 'b1;
axi_awready <= 1 'b0;
end
else
begin
axi_awready <= 1 'b0;
end
end
end

// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.

always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1 'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end

// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.

always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1 'b0 )
begin
axi_wready <= 1 'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1 'b1;
end
else
begin
axi_wready <= 1 'b0;
end
end
end

assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;

always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1 'b0 )begin
slv_reg0 <= 0;
end
else if(slv_reg_wren)begin
if (axi_awaddr[3:2] == 2 'd0)
slv_reg0[31:0] <= S_AXI_WDATA[31:0];
else if (axi_awaddr[3:2] == 2 'd1)
slv_reg1[31:0] <= S_AXI_WDATA[31:0];
end else begin
slv_reg0 <= 0;
slv_reg1 <= slv_reg1;
end
end

// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.

always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1 'b0 )
begin
axi_bvalid<=0;
axi_bresp<=2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1 'b1;
axi_bresp  <= 2 'b0; // 'OKAY ' response
end                   // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1 'b0;
end
end
end
end

// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.

always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1 'b0 )
begin
axi_arready <= 1 'b0;
axi_araddr  <= 32 'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1 'b1;
// Read address latching
axi_araddr  <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1 'b0;
end
end
end

// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1 'b0 )
begin
axi_rvalid <= 0;
axi_rresp  <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1 'b1;
axi_rresp  <= 2 'b0; // 'OKAY ' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1 'b0;
end
end
end

// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
if(axi_awaddr[3:2] == 2 'd0)
reg_data_out[31 : 0] <= slv_reg0;
else if(axi_awaddr[3:2] == 2 'd1)
reg_data_out[31 : 0] <= slv_reg1;
else
reg_data_out <= reg_data_out;

// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1 'b0 )
begin
axi_rdata  <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden) begin
axi_rdata <= reg_data_out;     // register read data
end
end
end

// Add user logic here

reg  [4 :0] i;
reg  [4 :0] j;
reg  [4 :0] k;
assign xdma_irq_req_o = xdma_irq_req;

assign user_irq_en_o = slv_reg1[31];

wire [XMDA_REQ_NUM-1:0] xdma_irq_ack = slv_reg0[XMDA_REQ_NUM-1:0];

always @( posedge S_AXI_ACLK ) begin
if ( S_AXI_ARESETN == 1 'b0 || user_irq_en_o == 1 'b0 )begin
user_irq_req_r1 = 0;
user_irq_req_r2 = 0;
user_irq_req_r3 = 0;
end
else begin
user_irq_req_r1 <= user_irq_req_i;
user_irq_req_r2 <= user_irq_req_r1;
user_irq_req_r3 <= user_irq_req_r2;
end
end
always @( posedge S_AXI_ACLK ) begin
if ( S_AXI_ARESETN == 1 'b0 || user_irq_en_o == 1 'b0)begin
j <= 5 'd0;
user_irq_req <= 0;
end
else begin
for(j = 0; j <=XMDA_REQ_NUM-1; j = j +1 )
user_irq_req[j] <= !user_irq_req_r3[j] & user_irq_req_r2[j];
end
end

always @( posedge S_AXI_ACLK ) begin
if ( S_AXI_ARESETN == 1 'b0 || user_irq_en_o == 1 'b0)begin
i <= 5 'd0;
xdma_irq_req <= 0;
end
else begin
for(i = 0; i <=XMDA_REQ_NUM-1; i = i +1 )begin
if(xdma_irq_ack[i]) begin
xdma_irq_req[i] <= 1 'b0;
end
else if(user_irq_req[i])begin
xdma_irq_req[i] <= 1 'b1;
end
end
end
end
// User logic ends

endmodule
复制代码

wireaxi_aclk;
wireaxi_aresetn;
wireuser_irq_en_o;
reg [21:0]timer_cnt;

always@(posedgeaxi_aclk)begin
  if(!axi_aresetn||!user_irq_en_o)begin
      timer_cnt<=22'd0;
  end
  elsebegin
      timer_cnt<=timer_cnt+1'b1;
  end
end

regtimer_r1,timer_r2;
wireinter=!timer_r2&&timer_r1;

always@(posedgeaxi_aclk)begin
  if(!axi_aresetn||!user_irq_en_o)begin
      timer_r1<=1'd0;
      timer_r2<=1'd0;
  end
  elsebegin
      timer_r1<=timer_cnt[20];
      timer_r2<=timer_r1;
  end
end

reg[1:0]int_p;
reg[3:0]user_irq_req_i;

always@(posedgeaxi_aclk)begin
  if(!axi_aresetn||!user_irq_en_o)begin
      int_p[1:0] <=4'd0;
      user_irq_req_i<=4'd0;
  end
  elsebegin
    if(inter) int_p<=int_p+1'b1;
    user_irq_req_i<=4'd0;
    user_irq_req_i[int_p]<=1'b1; 
  end
end
复制代码

#include<Windows.h>
#include<assert.h>
#include<stdlib.h>
#include<stdio.h>
#include<strsafe.h>
#include<stdint.h>
#include<SetupAPI.h>
#include<INITGUID.H>
#include<WinIoCtl.h>
//#include<AtlBase.h>
#include<io.h>
#include"xdma_public.h"

#pragmacomment(lib,"setupapi.lib")
#pragmawarning(disable:4996)
BYTE start_en;
HANDLEh_user;
DWORD user_irq_ack[1];
char base_path[MAX_PATH+1]="";

#defineMAX_BYTES_PER_TRANSFER0x800000

staticintverbose_msg(constchar*constfmt,...){

  intret=0;
  va_listargs;
  if(1){
    va_start(args,fmt);
    ret=vprintf(fmt,args);
    va_end(args);
  }
  returnret;

}
staticBYTE*allocate_buffer(size_tsize,size_talignment){

  if(size==0){
    size=4;
  }

  if(alignment==0){
    SYSTEM_INFOsys_info;
    GetSystemInfo(&sys_info);
    alignment=sys_info.dwPageSize;
    //printf("alignment=%d\n",alignment);
  }
  verbose_msg("Allocatinghost-sidebufferofsize%d,alignedto%dbytes\n",size,alignment);
  return(BYTE*)_aligned_malloc(size,alignment);

}

staticintget_devices(GUIDguid,char*devpath,size_tlen_devpath){

  SP_DEVICE_INTERFACE_DATAdevice_interface;
  PSP_DEVICE_INTERFACE_DETAIL_DATAdev_detail;
  DWORDindex;
  HDEVINFOdevice_info;
  wchar_ttmp[256];
  device_info=SetupDiGetClassDevs((LPGUID)&guid,NULL,NULL,DIGCF_PRESENT|DIGCF_DEVICEINTERFACE);
  if(device_info==INVALID_HANDLE_VALUE){
    fprintf(stderr,"GetDevicesINVALID_HANDLE_VALUE\n");
    exit(-1);
  }

  device_interface.cbSize=sizeof(SP_DEVICE_INTERFACE_DATA);
  //enumeratethroughdevices

  for(index=0;SetupDiEnumDeviceInterfaces(device_info,NULL,&guid,index,&device_interface);++index){

    //getrequiredbuffersize
    ULONGdetailLength=0;
    if(!SetupDiGetDeviceInterfaceDetail(device_info,&device_interface,NULL,0,&detailLength,NULL)&&GetLastError()!=ERROR_INSUFFICIENT_BUFFER){
      fprintf(stderr,"SetupDiGetDeviceInterfaceDetail-getlengthfailed\n");
      break;
    }

    //allocatespacefordeviceinterfacedetail
    dev_detail=(PSP_DEVICE_INTERFACE_DETAIL_DATA)HeapAlloc(GetProcessHeap(),HEAP_ZERO_MEMORY,detailLength);
    if(!dev_detail){
      fprintf(stderr,"HeapAllocfailed\n");
      break;
    }
    dev_detail->cbSize=sizeof(SP_DEVICE_INTERFACE_DETAIL_DATA);

    //getdeviceinterfacedetail
    if(!SetupDiGetDeviceInterfaceDetail(device_info,&device_interface,dev_detail,detailLength,NULL,NULL)){
      fprintf(stderr,"SetupDiGetDeviceInterfaceDetail-getdetailfailed\n");
      HeapFree(GetProcessHeap(),0,dev_detail);
      break;
    }

    StringCchCopy(tmp,len_devpath,dev_detail->DevicePath);
    wcstombs(devpath,tmp,256);
    HeapFree(GetProcessHeap(),0,dev_detail);
  }

  SetupDiDestroyDeviceInfoList(device_info);

  returnindex;
}

HANDLEopen_devices(char*device_base_path,char*device_name,DWORDaccessFlags)
{
  chardevice_path[MAX_PATH+1]="";
  wchar_tdevice_path_w[MAX_PATH+1];
  HANDLEh;

  //extenddevicepathtoincludetargetdevicenode(xdma_control,xdma_useretc)
  verbose_msg("Devicebasepath:%s\n",device_base_path);
  strcpy_s(device_path,sizeofdevice_path,device_base_path);
  strcat_s(device_path,sizeofdevice_path,device_name);
  verbose_msg("Devicenode:%s\n",device_name);
  //opendevicefile
  mbstowcs(device_path_w,device_path,sizeof(device_path));
  h=CreateFile(device_path_w,accessFlags,0,NULL,OPEN_EXISTING,FILE_ATTRIBUTE_NORMAL,NULL);
  if(h==INVALID_HANDLE_VALUE)
  {
    fprintf(stderr,"Erroropeningdevice,win32errorcode:%ld\n",GetLastError());
  }

  returnh;
}

staticintread_device(HANDLEdevice,longaddress,DWORDsize,BYTE*buffer)
{
  DWORDrd_size=0;

  unsignedinttransfers;
  unsignedinti;
  if(INVALID_SET_FILE_POINTER==SetFilePointer(device,address,NULL,FILE_BEGIN)){
    fprintf(stderr,"Errorsettingfilepointer,win32errorcode:%ld\n",GetLastError());
    return-3;
  }
  transfers=(unsignedint)(size/MAX_BYTES_PER_TRANSFER);
  for(i=0;i<transfers;i++)
  {
    if(!ReadFile(device,(void*)(buffer+i*MAX_BYTES_PER_TRANSFER),(DWORD)MAX_BYTES_PER_TRANSFER,&rd_size,NULL))
    {
      return-1;
    }
    if(rd_size!=MAX_BYTES_PER_TRANSFER)
    {
      return-2;
    }
  }
  if(!ReadFile(device,(void*)(buffer+i*MAX_BYTES_PER_TRANSFER),(DWORD)(size-i*MAX_BYTES_PER_TRANSFER),&rd_size,NULL))
  {
    return-1;
  }
  if(rd_size!=(size-i*MAX_BYTES_PER_TRANSFER))
  {
    return-2;
  }

  returnsize;
}

staticintwrite_device(HANDLEdevice,longaddress,DWORDsize,BYTE*buffer)
{
  DWORDwr_size=0;
  unsignedinttransfers;
  unsignedinti;
  transfers=(unsignedint)(size/MAX_BYTES_PER_TRANSFER);
  //printf("transfers=%d\n",transfers);
  if(INVALID_SET_FILE_POINTER==SetFilePointer(device,address,NULL,FILE_BEGIN)){
    fprintf(stderr,"Errorsettingfilepointer,win32errorcode:%ld\n",GetLastError());
    return-3;
  }
  for(i=0;i<transfers;i++)
  {
    if(!WriteFile(device,(void*)(buffer+i*MAX_BYTES_PER_TRANSFER),MAX_BYTES_PER_TRANSFER,&wr_size,NULL))
    {
      return-1;
    }
    if(wr_size!=MAX_BYTES_PER_TRANSFER)
    {
      return-2;
    }
  }
  if(!WriteFile(device,(void*)(buffer+i*MAX_BYTES_PER_TRANSFER),(DWORD)(size-i*MAX_BYTES_PER_TRANSFER),&wr_size,NULL))
  {
    return-1;
  }
  if(wr_size!=(size-i*MAX_BYTES_PER_TRANSFER))
  {
    return-2;
  }
  returnsize;
}

DWORDWINAPIthread_event0(LPVOIDlpParam)
{
  BYTEval0[1]="";
  DWORDi=0;
  BYTEstatu;
  char*device_name1="\\event_0";
  HANDLEh_event0=open_devices(base_path,device_name1,GENERIC_READ);
    while(1)
    {
      if(start_en){
        read_device(h_event0,0,1,val0);//waiteirq
        Sleep(1);
        if(val0[0]==1)
          printf("event_0done!\n");
        else
          printf("event_0timeout!\n");
        i++;

      }
  }
  CloseHandle(h_event0);
  return0;
}

DWORDWINAPIthread_event1(LPVOIDlpParam)
{
  BYTEval0[1]="";
  DWORDi=0;
  BYTEstatu;
  char*device_name1="\\event_1";
  HANDLEh_event1=open_devices(base_path,device_name1,GENERIC_READ);
  while(1)
  {
    if(start_en){
      read_device(h_event1,0,1,val0);//waiteirq
      Sleep(1);
      if(val0[0]==1)
        printf("event_1done!\n");
      else
        printf("event_1timeout!\n");
      i++;

    }
  }
  CloseHandle(h_event1);
  return0;
}

DWORDWINAPIthread_event2(LPVOIDlpParam)
{
  BYTEval0[1]="";
  DWORDi=0;
  BYTEstatu;
  char*device_name1="\\event_2";
  HANDLEh_event2=open_devices(base_path,device_name1,GENERIC_READ);
  while(1)
  {
    if(start_en){
      read_device(h_event2,0,1,val0);//waiteirq
      Sleep(1);
      if(val0[0]==1)
        printf("event_2done!\n");
      else
        printf("event_2timeout!\n");
      i++;

    }
  }
  CloseHandle(h_event2);
  return0;
}

DWORDWINAPIthread_event3(LPVOIDlpParam)
{
  BYTEval0[1]="";
  DWORDi=0;
  BYTEstatu;
  char*device_name1="\\event_3";
  HANDLEh_event3=open_devices(base_path,device_name1,GENERIC_READ);
  while(1)
  {
    if(start_en){
      read_device(h_event3,0,1,val0);//waiteirq
      Sleep(1);
      if(val0[0]==1)
        printf("event_3done!\n");
      else
        printf("event_3timeout!\n");
      i++;

    }
  }
  CloseHandle(h_event3);
  return0;
}

int__cdeclmain(intargc,char*argv[])
{

  HANDLEh_event0;
  HANDLEh_event1;
  HANDLEh_event2;
  HANDLEh_event3;
  HANDLEh_event4;
  HANDLEh_event5;
  HANDLEh_event6;
HANDLEh_event7;

  char*device_name="\\user";
  DWORDnum_devices=get_devices(GUID_DEVINTERFACE_XDMA,base_path,sizeof(base_path));

  verbose_msg("Devicesfound:%d\n",num_devices);
  if(num_devices<1)
  {
    printf("error\n");
  }

  h_user=open_devices(base_path,device_name,GENERIC_READ|GENERIC_WRITE);
  if(h_user==INVALID_HANDLE_VALUE)
  {
    fprintf(stderr,"Erroropeningdevice,win32errorcode:%ld\n",GetLastError());
  }

  h_event0=CreateThread(NULL,0,thread_event0,NULL,0,NULL);
  h_event1=CreateThread(NULL,0,thread_event1,NULL,0,NULL);
  h_event2=CreateThread(NULL,0,thread_event2,NULL,0,NULL);
  h_event3=CreateThread(NULL,0,thread_event3,NULL,0,NULL);

  user_irq_ack[0]=0xffff0000;
  write_device(h_user,0x00004,4,(BYTE*)user_irq_ack);//startirq
  start_en=1;

  printf("start\n");
  WaitForSingleObject(h_event0,INFINITE);
  WaitForSingleObject(h_event1,INFINITE);
  WaitForSingleObject(h_event2,INFINITE);
  WaitForSingleObject(h_event3,INFINITE);

  user_irq_ack[0]=0x00000000;
  write_device(h_user,0x00004,4,(BYTE*)user_irq_ack);//stop irq
  CloseHandle(h_user);
  CloseHandle(h_event0);
  CloseHandle(h_event1);
  CloseHandle(h_event2);
  CloseHandle(h_event3);
  return0;
}
复制代码

以上程序设置了4个中断事件，每个事件开启了一个线程，当中断等待的时候线程是挂起的，当中断产生后，继续执行线程。对于XDMA最大可以支持32个中断

3:XDMA中断测试

执行xdma_event.exe程序

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​

可以看到运行结果是4个中断事件，实际上XMDA最大支持16个中断事件。更多的中断时间可以更好的发挥CPU多核多线程的性能。

看FPGA抓的波形信号

​

好了，到此XDMA的PCIE方案核心内容就已经讲完了。XILINX官方给的资料往往没有细化，我们米联客已经对以上驱动稍加修改，以更好地支持中断。

​