[Place 30-510] Unroutable Placement! A GTHE_COMMON / GTHE_CHANNEL clock component pair is not placed in a routable site pair. The GTHE_COMMON component can use the dedicated path between the GTHE_COMMON and the GTHE_CHANNEL if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[25].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/qpll0outclk_out[0]] >
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[25].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST (GTHE3_COMMON.QPLL0OUTCLK) is provisionally placed by clockplacer on GTHE3_COMMON_X1Y3 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[25].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.QPLL0CLK) is locked to GTHE3_CHANNEL_X1Y2 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[25].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.QPLL0CLK) is locked to GTHE3_CHANNEL_X1Y3 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[25].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.QPLL0CLK) is locked to GTHE3_CHANNEL_X1Y1 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[25].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.QPLL0CLK) is locked to GTHE3_CHANNEL_X1Y7 (in SLR 0)
The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.
Clock Rule: rule_bufds_gthchannel_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTHChannel must both be placed in the same or adjacent two clock
regions (top/bottom)
my_pcie/system_pcie4_i/util_ds_buf/U0/USE_IBUFDS_GTE3.GEN_IBUFDS_GTE3[0].IBUFDS_GTE3_I (IBUFDS_GTE3.O) is locked to GTHE3_COMMON_X1Y1 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[25].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.GTREFCLK0) is locked to GTHE3_CHANNEL_X1Y2 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[25].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.GTREFCLK0) is locked to GTHE3_CHANNEL_X1Y3 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[25].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.GTREFCLK0) is locked to GTHE3_CHANNEL_X1Y1 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[25].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.GTREFCLK0) is locked to GTHE3_CHANNEL_X1Y7 (in SLR 0)
Clock Rule: rule_bufds_gthcommon_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTHCommon must both be placed in the same or adjacent two clock
regions (top/bottom)
my_pcie/system_pcie4_i/util_ds_buf/U0/USE_IBUFDS_GTE3.GEN_IBUFDS_GTE3[0].IBUFDS_GTE3_I (IBUFDS_GTE3.O) is locked to GTHE3_COMMON_X1Y1 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[25].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST (GTHE3_COMMON.GTREFCLK01) is provisionally placed by clockplacer on GTHE3_COMMON_X1Y3 (in SLR 0)
Clock Rule: rule_gt_bufggt
Status: PASS
Rule Description: A GT driving a BUFG_GT must be placed in the same clock region of the device as the
BUFG
my_pcie/system_pcie4_i/util_ds_buf/U0/USE_IBUFDS_GTE3.GEN_IBUFDS_GTE3[0].IBUFDS_GTE3_I (IBUFDS_GTE3.ODIV2) is locked to GTHE3_COMMON_X1Y1 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/bufg_gt_sysclk (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X1Y27 (in SLR 0)
Clock Rule: rule_gthbufds_bufgsync
Status: PASS
Rule Description: A BUFDS drives a BUFG_GT_SYNC pin must both be in the same clock region and both
have to be in specific sites.
my_pcie/system_pcie4_i/util_ds_buf/U0/USE_IBUFDS_GTE3.GEN_IBUFDS_GTE3[0].IBUFDS_GTE3_I (IBUFDS_GTE3.ODIV2) is locked to GTHE3_COMMON_X1Y1 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/sync_sys_clk (BUFG_GT_SYNC.CLK) is provisionally placed by clockplacer on BUFG_GT_SYNC_X1Y11 (in SLR 0)
Clock Rule: rule_bufgsync_bufg_withGTDriver
Status: PASS
Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
as the BUFG_GT
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/sync_sys_clk (BUFG_GT_SYNC.CESYNC) is provisionally placed by clockplacer on BUFG_GT_SYNC_X1Y11 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/bufg_gt_sysclk (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X1Y27 (in SLR 0)
Clock Rule: rule_gthcommon_gthchannel
Status: FAIL
Rule Description: A GTHCommon driving a GTHChannel must both be in the same clock region
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[25].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST (GTHE3_COMMON.QPLL1OUTCLK) is provisionally placed by clockplacer on GTHE3_COMMON_X1Y3 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[25].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.QPLL1CLK) is locked to GTHE3_CHANNEL_X1Y2 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[25].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.QPLL1CLK) is locked to GTHE3_CHANNEL_X1Y3 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[25].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.QPLL1CLK) is locked to GTHE3_CHANNEL_X1Y1 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[25].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.QPLL1CLK) is locked to GTHE3_CHANNEL_X1Y7 (in SLR 0)
ERROR: The above is also an illegal clock rule
Workaround: < set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[25].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/qpll1outclk_out[0]] >
Clock Rule: rule_gt_bufggt
Status: PASS
Rule Description: A GT driving a BUFG_GT must be placed in the same clock region of the device as the
BUFG
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[25].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.TXOUTCLK) is locked to GTHE3_CHANNEL_X1Y7 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/bufg_mcap_clk (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X1Y26 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/phy_clk_i/bufg_gt_coreclk (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X1Y25 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/phy_clk_i/bufg_gt_pclk (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X1Y24 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X1Y47 (in SLR 0)
Clock Rule: rule_gthchannel_bufgsync_tx
Status: PASS
Rule Description: A GTHChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
both have to be in specific sites.
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[25].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST (GTHE3_CHANNEL.TXOUTCLK) is locked to GTHE3_CHANNEL_X1Y7 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[25].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC (BUFG_GT_SYNC.CLK) is provisionally placed by clockplacer on BUFG_GT_SYNC_X1Y18 (in SLR 0)
Clock Rule: rule_bufgsync_bufg_withGTDriver
Status: PASS
Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
as the BUFG_GT
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/system_pcie4_xdma_0_0_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.system_pcie4_xdma_0_0_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[25].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC (BUFG_GT_SYNC.CESYNC) is provisionally placed by clockplacer on BUFG_GT_SYNC_X1Y18 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/bufg_mcap_clk (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X1Y26 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/phy_clk_i/bufg_gt_pclk (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X1Y24 (in SLR 0)
my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X1Y47 (in SLR 0)
and my_pcie/system_pcie4_i/xdma_0/inst/pcie3_ip_i/inst/gt_top_i/phy_clk_i/bufg_gt_coreclk (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X1Y25 (in SLR 0)
微信客服01
QQ售前
发表
PCIE专题
679 人阅读
|
2 人回复
提升卡
置顶卡
沉默卡
喧嚣卡
变色卡
千斤顶
照妖镜