我们要对图像进行处理，很多图像算法一般都是要进行卷积运算，而卷积则是要通过窗口来实现，窗口则是我们做卷积的基本模板。下面的模型是我们搭建3x3窗口的模型，这里我们的绿色模块3LineBuffer是我们算法的核心，我们将其模块进行打包为一个块儿。
3LineBuffer打包为一个模块，下面右侧则是该模块的内部模块搭建，这里的3x3窗口的搭建跟我们的图像分辨率有关，我们通过仿真来进行调试，通过修改Delay1、Delay2和Delay3的延时数来进行调节，从而完成调试工作。下面的分辨率为1920x1080的分辨率的3x3窗口。
我们运行模块的仿真，验证搭建的3x3窗口的正确性，可以查看经过图像算法处理后的效果，也可以通过viewsignals来调用Vivado Simulation来查看波形的正确性。在验证3x3窗口的正确性后，我们就可以通过点击SystemGenerator模块的Generate来生成相应的代码，下面是我们生成代码的文件及文件夹：
我们打开window3by3.v文件，在其文件中找到同名模块window3by3 module，通过加入控制信号和使能信号来控制我们算法运行方式，其代码如下：
//Generated from Simulink block "window3by3"
(* core_generation_info = "window3by3,sysgen_core_2015_2,{compilation=HDLNetlist,block_icon_display=Default,family=zynq,part=xc7z020,speed=-1,package=clg484,synthesis_tool=Vivado,synthesis_language=verilog,hdl_library=work,proj_type=Vivado,synth_file=VivadoSynthesis Defaults,impl_file=Vivado ImplementationDefaults,clock_loc=,clock_wrapper=ClockEnables,directory=E:/matlab/Sys_Gen_pian/For_prj/window3by3/netlist,testbench=1,create_interface_document=1,ce_clr=0,base_system_period_hardware=5,dcm_input_clock_period=100,base_system_period_simulink=1,sim_time=10,sim_status=1,}"*)
modulewindow3by3 (
input clk,
//Image data prepred to be processd
input vid_hblank, //PreparedImage data vsync valid signal
input vid_vblank, //Prepared Image data href vaild signal
input vid_active_video,
input [7:0] per_img_Y, //Prepared Image brightness input
//Image data has been processd
output matrix_frame_href, //Prepared Image data vsync valid signal
output matrix_frame_vsync, //Prepared Image data href vaild signal
output matrix_frame_clken,
output [7:0] matrix_p11, matrix_p12, matrix_p13, //3X3 Matrix output
output [7:0] matrix_p21, matrix_p22, matrix_p23,
output [7:0] matrix_p31, matrix_p32, matrix_p33
);
wire clk_1_net;
wire ce_1_net;
wire clk_net;
wire counter_en_net;
wire we_net;
wire [7:0] per_img_y_net;
wire [7:0] matrix_p11_net;
wire [7:0] matrix_p12_net;
wire [7:0] matrix_p13_net;
wire [7:0] matrix_p21_net;
wire [7:0] matrix_p22_net;
wire [7:0] matrix_p23_net;
wire [7:0] matrix_p31_net;
wire [7:0] matrix_p32_net;
wire [7:0] matrix_p33_net;
assign clk_net = clk;
assign counter_en_net = vid_active_video;
assign we_net = vid_active_video;
assign per_img_y_net = per_img_Y;
assign matrix_p11 = matrix_p11_net;
assign matrix_p12 = matrix_p12_net;
assign matrix_p13 = matrix_p13_net;
assign matrix_p21 = matrix_p21_net;
assign matrix_p22 = matrix_p22_net;
assign matrix_p23 = matrix_p23_net;
assign matrix_p31 = matrix_p31_net;
assign matrix_p32 = matrix_p32_net;
assign matrix_p33 = matrix_p33_net;
window3by3_struct window3by3_struct (
.clk_1(clk_1_net),
.ce_1(ce_1_net),
.counter_en(counter_en_net),
.we(we_net),
.per_img_y(per_img_y_net),
.matrix_p11(matrix_p11_net),
.matrix_p12(matrix_p12_net),
.matrix_p13(matrix_p13_net),
.matrix_p21(matrix_p21_net),
.matrix_p22(matrix_p22_net),
.matrix_p23(matrix_p23_net),
.matrix_p31(matrix_p31_net),
.matrix_p32(matrix_p32_net),
.matrix_p33(matrix_p33_net)
);
default_clock_driver_window3by3default_clock_driver_window3by3 (
.sysclk(clk_net),
.sysce(vid_active_video), // enable signal
.sysce_clr(1'b0),
.clk_1(clk_1_net),
.ce_1(ce_1_net)
);
//lag 2 clocks signal sync
reg [1:0] matrix_frame_href_r;
reg [1:0] matrix_frame_vsync_r;
reg [1:0] matrix_frame_clken_r;
always@(posedge clk)
begin
matrix_frame_href_r <= {matrix_frame_href_r[0] ,vid_hblank};
matrix_frame_vsync_r <= {matrix_frame_vsync_r[0] ,vid_vblank};
matrix_frame_clken_r <= {matrix_frame_clken_r[0] ,vid_active_video};
end
// delay one clock
// wire read_frame_clken = matrix_frame_clken_r[0]; //RAM read enable
// delay two clock
assign matrix_frame_href = matrix_frame_href_r[1];
assign matrix_frame_vsync= matrix_frame_vsync_r[1];
assign matrix_frame_clken= matrix_frame_clken_r[1];
endmodule
当我们要搭建5x5窗口，我们可以通过对3x3窗口进行改造，将两个3x3窗口进行组合，其中第一个3x3窗口的最后一个输出信号端输出给第二个3x3窗口的第一个信号输入端，就可以构建成5x5窗口的实现，同理可以构造7x7、9x9等奇数型的窗口
下面为5x5窗口的SystemGenerator生成代码，用户可以根据下面生成的代码，添加控制信号来对代码进行合理控制。
//Generated from Simulink block " window5by5"
(* core_generation_info ="gausslap,sysgen_core_2015_2,{compilation=HDL Netlist,block_icon_display=Default,family=zynq,part=xc7z020,speed=-1,package=clg484,synthesis_tool=Vivado,synthesis_language=verilog,hdl_library=work,proj_type=Vivado,synth_file=VivadoSynthesis Defaults,impl_file=Vivado ImplementationDefaults,clock_loc=,clock_wrapper=ClockEnables,directory=./netlist,testbench=1,create_interface_document=1,ce_clr=0,base_system_period_hardware=5,dcm_input_clock_period=100,base_system_period_simulink=1,sim_time=2.07362e+06,sim_status=1,}"*)
modulewindow5by5 (
clk,
gateway_in1,
gateway_in,
matrix_p11,
matrix_p41,
matrix_p43,
matrix_p45,
matrix_p51,
matrix_p52,
matrix_p53,
matrix_p54,
matrix_p55,
matrix_p12,
matrix_p13,
matrix_p14,
matrix_p15,
matrix_p21,
matrix_p23,
matrix_p25,
matrix_p31,
matrix_p32,
matrix_p33,
matrix_p34,
matrix_p35
);
input clk;
input gateway_in1;
input [7:0] gateway_in;
output [7:0] matrix_p11;
output [7:0] matrix_p41;
output [7:0] matrix_p43;
output [7:0] matrix_p45;
output [7:0] matrix_p51;
output [7:0] matrix_p52;
output [7:0] matrix_p53;
output [7:0] matrix_p54;
output [7:0] matrix_p55;
output [7:0] matrix_p12;
output [7:0] matrix_p13;
output [7:0] matrix_p14;
output [7:0] matrix_p15;
output [7:0] matrix_p21;
output [7:0] matrix_p23;
output [7:0] matrix_p25;
output [7:0] matrix_p31;
output [7:0] matrix_p32;
output [7:0] matrix_p33;
output [7:0] matrix_p34;
output [7:0] matrix_p35;
wire clk_1_net;
wire ce_1_net;
wire clk_net;
wire gateway_in1_net;
wire [7:0] gateway_in_net;
wire [7:0] matrix_p11_net;
wire [7:0] matrix_p41_net;
wire [7:0] matrix_p43_net;
wire [7:0] matrix_p45_net;
wire [7:0] matrix_p51_net;
wire [7:0] matrix_p52_net;
wire [7:0] matrix_p53_net;
wire [7:0] matrix_p54_net;
wire [7:0] matrix_p55_net;
wire [7:0] matrix_p12_net;
wire [7:0] matrix_p13_net;
wire [7:0] matrix_p14_net;
wire [7:0] matrix_p15_net;
wire [7:0] matrix_p21_net;
wire [7:0] matrix_p23_net;
wire [7:0] matrix_p25_net;
wire [7:0] matrix_p31_net;
wire [7:0] matrix_p32_net;
wire [7:0] matrix_p33_net;
wire [7:0] matrix_p34_net;
wire [7:0] matrix_p35_net;
assign clk_net = clk;
assign gateway_in1_net = gateway_in1;
assign gateway_in_net = gateway_in;
assign matrix_p11 = matrix_p11_net;
assign matrix_p41 = matrix_p41_net;
assign matrix_p43 = matrix_p43_net;
assign matrix_p45 = matrix_p45_net;
assign matrix_p51 = matrix_p51_net;
assign matrix_p52 = matrix_p52_net;
assign matrix_p53 = matrix_p53_net;
assign matrix_p54 = matrix_p54_net;
assign matrix_p55 = matrix_p55_net;
assign matrix_p12 = matrix_p12_net;
assign matrix_p13 = matrix_p13_net;
assign matrix_p14 = matrix_p14_net;
assign matrix_p15 = matrix_p15_net;
assign matrix_p21 = matrix_p21_net;
assign matrix_p23 = matrix_p23_net;
assign matrix_p25 = matrix_p25_net;
assign matrix_p31 = matrix_p31_net;
assign matrix_p32 = matrix_p32_net;
assign matrix_p33 = matrix_p33_net;
assign matrix_p34 = matrix_p34_net;
assign matrix_p35 = matrix_p35_net;
window5by5_struct window5by5_struct (
.clk_1(clk_1_net),
.ce_1(ce_1_net),
.gateway_in1(gateway_in1_net),
.gateway_in(gateway_in_net),
.matrix_p11(matrix_p11_net),
.matrix_p41(matrix_p41_net),
.matrix_p43(matrix_p43_net),
.matrix_p45(matrix_p45_net),
.matrix_p51(matrix_p51_net),
.matrix_p52(matrix_p52_net),
.matrix_p53(matrix_p53_net),
.matrix_p54(matrix_p54_net),
.matrix_p55(matrix_p55_net),
.matrix_p12(matrix_p12_net),
.matrix_p13(matrix_p13_net),
.matrix_p14(matrix_p14_net),
.matrix_p15(matrix_p15_net),
.matrix_p21(matrix_p21_net),
.matrix_p23(matrix_p23_net),
.matrix_p25(matrix_p25_net),
.matrix_p31(matrix_p31_net),
.matrix_p32(matrix_p32_net),
.matrix_p33(matrix_p33_net),
.matrix_p34(matrix_p34_net),
.matrix_p35(matrix_p35_net)
);
default_clock_driver_ window5by5 default_clock_driver_ window5by5 (
.sysclk(clk_net),
.sysce(1'b1),
.sysce_clr(1'b0),
.clk_1(clk_1_net),
.ce_1(ce_1_net)
);
endmodule
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