`timescale 1ns / 1ps

/*******************************MILIANKE*******************************
*Company : MiLianKe Electronic Technology Co., Ltd.
*WebSite:https://www.milianke.com
*TechWeb:https://www.uisrc.com
*tmall-shop:https://milianke.tmall.com
*jd-shop:https://milianke.jd.com
*taobao-shop1: https://milianke.taobao.com
*Create Date : 2021/10/15
*File Name : pcie_top.v
*Description :
*Declaration :
*The reference demo provided by Milianke is only used for learning.
*We cannot ensure that the demo itself is free of bugs, so users
*should be responsible for the technical problems and consequences
*caused by the use of their own products.
*Copyright: Copyright (c) MiLianKe
*All rights reserved.
*Revision : 1.0
*Signal description
*1) _i input
*2) _o output
*3) _n activ low
*4) _dg debug signal
*5) _r delay or register
*6) _s state mechine
*********************************************************************/
module pcie_top
(
output [14:0]DDR3_addr,
output [2:0]DDR3_ba,
output DDR3_cas_n,
output [0:0]DDR3_ck_n, 
output [0:0]DDR3_ck_p, 
output [0:0]DDR3_cke,  
output [0:0]DDR3_cs_n, 
output [7:0]DDR3_dm,   
inout [63:0]DDR3_dq,   
inout [7:0]DDR3_dqs_n, 
inout [7:0]DDR3_dqs_p, 
output [0:0]DDR3_odt,
output DDR3_ras_n,
output DDR3_reset_n, 
output DDR3_we_n,
input  sysclk_p, 
input  sysclk_n,

input  [7 :0]pcie_mgt_rxn,
input  [7 :0]pcie_mgt_rxp,
output [7 :0]pcie_mgt_txn,
output [7 :0]pcie_mgt_txp,
input  [0 :0]pcie_ref_clk_n,
input  [0 :0]pcie_ref_clk_p,
input pcie_rst_n
);

wire sysclk;
IBUFDS CLK_U(.I(sysclk_p),.IB(sysclk_n),.O(sysclk));

wire axi_aclk;
wire user_irq_en_o;
reg  [21:0]timer_cnt;
reg  timer_r1,timer_r2;
reg [1:0]int_p;
reg [3:0]user_irq_req_i;
wire inter = !timer_r2 && timer_r1;

always @(posedge axi_aclk)begin
if(user_irq_en_o == 1 'b0)begin
timer_cnt <= 22 'd0;
end
else begin
timer_cnt <= timer_cnt + 1 'b1;
end
end
always @(posedge axi_aclk)begin
if(user_irq_en_o == 1 'b0)begin
timer_r1 <= 1 'd0;
timer_r2 <= 1 'd0;
end
else begin
timer_r1 <= timer_cnt[20];
timer_r2 <= timer_r1;
end
end


always @(posedge axi_aclk)begin
if(user_irq_en_o == 1 'b0)begin
int_p[1:0]  <= 4 'd0;
user_irq_req_i <= 4 'd0;
end
else begin
if(inter)  int_p <= int_p + 1 'b1;
user_irq_req_i <= 4 'd0;
user_irq_req_i[int_p] <= 1 'b1;
end
end

pcie_system pcie_system_i(
.DDR3_addr(DDR3_addr),
.DDR3_ba(DDR3_ba),
.DDR3_cas_n(DDR3_cas_n),
.DDR3_ck_n(DDR3_ck_n),
.DDR3_ck_p(DDR3_ck_p),
.DDR3_cke(DDR3_cke),
.DDR3_cs_n(DDR3_cs_n),
.DDR3_dm(DDR3_dm),
.DDR3_dq(DDR3_dq),
.DDR3_dqs_n(DDR3_dqs_n),
.DDR3_dqs_p(DDR3_dqs_p),
.DDR3_odt(DDR3_odt),
.DDR3_ras_n(DDR3_ras_n),
.DDR3_reset_n(DDR3_reset_n),
.DDR3_we_n(DDR3_we_n),

.pcie_mgt_rxn(pcie_mgt_rxn),
.pcie_mgt_rxp(pcie_mgt_rxp),
.pcie_mgt_txn(pcie_mgt_txn),
.pcie_mgt_txp(pcie_mgt_txp),
.pcie_ref_clk_n(pcie_ref_clk_n),
.pcie_ref_clk_p(pcie_ref_clk_p),
.pcie_rst_n(pcie_rst_n),
.axi_aclk(axi_aclk),
.user_irq_en_o(user_irq_en_o),
.user_irq_req_i(user_irq_req_i),
.sysclk(sysclk)
);


endmodule
复制代码

• rc = pci_enable_msix(pdev, lro->entry, req_nvec);
  

• #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0)
•   rc = pci_enable_msix(pdev, lro->entry, req_nvec);
• #else
•   rc = pci_enable_msix_range(pdev, lro->entry, req_nvec, req_nvec);
• #endif
  

• mmiowb();
  

• #if LINUX_VERSION_CODE <= KERNEL_VERSION(5, 1, 0)
• mmiowb();
• #endif