`timescale 1ns / 1ps /*******************************MILIANKE******************************* *Company : MiLianKe Electronic Technology Co., Ltd. *Create Date: 2021/10/15 *Module Name: *File Name: *Description: *config sensor resgister *The reference demo provided by Milianke is only used for learning. *We cannot ensure that the demo itself is free of bugs, so users *should be responsible for the technical problems and consequences *caused by the use of their own products. *Copyright: Copyright (c) MiLianKe *All rights reserved. *Revision: 1.0 *Signal description *1) I_ input *2) O_ output *3) IO_ input output *4) S_ system internal signal *5) _n activ low *6) _dg debug signal *7) _r delay or register *8) _s state mechine *********************************************************************/ module fdma_ddr_test( output [13:0]DDR3_0_addr, output [2 :0]DDR3_0_ba, output DDR3_0_cas_n, output [0 :0]DDR3_0_ck_n, output [0 :0]DDR3_0_ck_p, output [0 :0]DDR3_0_cke, output [0 :0]DDR3_0_cs_n, output [3 :0]DDR3_0_dm, inout [31:0]DDR3_0_dq, inout [3 :0]DDR3_0_dqs_n, inout [3 :0]DDR3_0_dqs_p, output [0 :0]DDR3_0_odt, output DDR3_0_ras_n, output DDR3_0_reset_n, output DDR3_0_we_n, input sysclk );
wire [31:0] fdma_raddr; reg fdma_rareq; wire fdma_rbusy; wire [127:0] fdma_rdata; wire [15:0] fdma_rsize; wire fdma_rvalid; wire [31:0] fdma_waddr; reg fdma_wareq; wire fdma_wbusy; wire [127:0] fdma_wdata; wire [15:0] fdma_wsize; wire fdma_wvalid; wire [0:0] fdma_rstn; wire ui_clk;
parameter TEST_MEM_SIZE = 32'd1024*1024*256; parameter FDMA_BURST_LEN = 16'd512; parameter ADDR_MEM_OFFSET = 0; parameter ADDR_INC = FDMA_BURST_LEN * 16;
parameter WRITE1 = 0; parameter WRITE2 = 1; parameter WAIT = 2; parameter READ1 = 3; parameter READ2 = 4;
reg [31: 0] t_data; reg [31: 0] fdma_waddr_r; reg [2 :0] T_S = 0;
assign fdma_waddr = fdma_waddr_r + ADDR_MEM_OFFSET; assign fdma_raddr = fdma_waddr;
assign fdma_wsize = FDMA_BURST_LEN; assign fdma_rsize = FDMA_BURST_LEN; assign fdma_wdata ={t_data,t_data,t_data,t_data};
reg [8:0] rst_cnt = 0;
always @(posedge ui_clk) if(~fdma_rstn)begin rst_cnt <=0; end else begin if(rst_cnt[8] == 1'b0) rst_cnt <= rst_cnt + 1'b1; else rst_cnt <= rst_cnt; end
always @(posedge ui_clk)begin if(rst_cnt[8] == 1'b0)begin T_S <=0; fdma_wareq <= 1'b0; fdma_rareq <= 1'b0; t_data<=0; fdma_waddr_r <=0; end else begin case(T_S) WRITE1:begin if(fdma_waddr_r==TEST_MEM_SIZE) fdma_waddr_r<=0; if(!fdma_wbusy)begin fdma_wareq <= 1'b1; t_data <= 0; end if(fdma_wareq&&fdma_wbusy)begin fdma_wareq <= 1'b0; T_S <= WRITE2; end end WRITE2:begin if(!fdma_wbusy) begin T_S <= WAIT; t_data <= 32'd0; end else if(fdma_wvalid) begin t_data <= t_data + 1'b1; end end WAIT:begin//not needed T_S <= READ1; end READ1:begin if(!fdma_rbusy)begin fdma_rareq <= 1'b1; t_data <= 0; end if(fdma_rareq&&fdma_rbusy)begin fdma_rareq <= 1'b0; T_S <= READ2; end end READ2:begin if(!fdma_rbusy) begin T_S <= WRITE1; t_data <= 32'd0; fdma_waddr_r <= fdma_waddr_r + ADDR_INC;//128/8=16 end else if(fdma_rvalid) begin t_data <= t_data + 1'b1; end end default: T_S <= WRITE1; endcase end end
reg test_error;
always @(posedge ui_clk)begin test_error <= (fdma_rvalid && (t_data[31:0] != fdma_rdata[31:0])); end
ila_0 ila_dbg ( .clk(ui_clk), .probe0({fdma_wdata[15:0],fdma_wareq,fdma_wvalid,fdma_wbusy}), .probe1({fdma_rdata[15:0],t_data[15:0],fdma_rvalid,fdma_rbusy,T_S,test_error}) );
system system_i (.DDR3_0_addr(DDR3_0_addr), .DDR3_0_ba(DDR3_0_ba), .DDR3_0_cas_n(DDR3_0_cas_n), .DDR3_0_ck_n(DDR3_0_ck_n), .DDR3_0_ck_p(DDR3_0_ck_p), .DDR3_0_cke(DDR3_0_cke), .DDR3_0_cs_n(DDR3_0_cs_n), .DDR3_0_dm(DDR3_0_dm), .DDR3_0_dq(DDR3_0_dq), .DDR3_0_dqs_n(DDR3_0_dqs_n), .DDR3_0_dqs_p(DDR3_0_dqs_p), .DDR3_0_odt(DDR3_0_odt), .DDR3_0_ras_n(DDR3_0_ras_n), .DDR3_0_reset_n(DDR3_0_reset_n), .DDR3_0_we_n(DDR3_0_we_n), .FDMA_S_0_i_fdma_raddr(fdma_raddr), .FDMA_S_0_i_fdma_rareq(fdma_rareq), .FDMA_S_0_o_fdma_rbusy(fdma_rbusy), .FDMA_S_0_o_fdma_rdata(fdma_rdata), .FDMA_S_0_i_fdma_rready(1'b1), .FDMA_S_0_i_fdma_rsize(fdma_rsize), .FDMA_S_0_o_fdma_rvalid(fdma_rvalid), .FDMA_S_0_i_fdma_waddr(fdma_waddr), .FDMA_S_0_i_fdma_wareq(fdma_wareq), .FDMA_S_0_o_fdma_wbusy(fdma_wbusy), .FDMA_S_0_i_fdma_wdata(fdma_wdata), .FDMA_S_0_i_fdma_wready(1'b1), .FDMA_S_0_i_fdma_wsize(fdma_wsize), .FDMA_S_0_o_fdma_wvalid(fdma_wvalid), .fdma_rstn(fdma_rstn), .sysclk(sysclk), .ui_clk(ui_clk)); endmodule | 
微信客服01
QQ售前
发表
AMD-FPGA
781 人阅读
|
0 人回复
提升卡
置顶卡
沉默卡
喧嚣卡
变色卡
千斤顶
照妖镜