`timescale 1 ps / 1 ps

module display(
input  clk_i,
output HDMI_CLK_P,
output HDMI_CLK_N,
output [2:0]HDMI_TX_P,
output [2:0]HDMI_TX_N
);

wire vid_rst,vid_clk,vid_vs,vid_hs,vid_de;
wire pclkx1,pclkx5,locked;
wire [7 :0]        rgb_r ,rgb_g ,rgb_b;
assign vid_clk = pclkx1;
assign vid_rst = locked;

clk_wiz_0 clk_wiz0_inst(.clk_out1(pclkx1),.clk_out2(pclkx5),.locked(locked),.clk_in1(clk_i)); 

uihdmitx #
(
.FAMILY("7FAMILY")                        
)
uihdmitx_inst
(
.RSTn_i(locked),
.HS_i(vid_hs),
.VS_i(vid_vs),
.VDE_i(vid_de),
.RGB_i({rgb_r,rgb_g,rgb_b}),
.PCLKX1_i(pclkx1),
.PCLKX2_5_i(1'b0),
.PCLKX5_i(pclkx5),
.TMDS_TX_CLK_P(HDMI_CLK_P),
.TMDS_TX_CLK_N(HDMI_CLK_N),
.TMDS_TX_P(HDMI_TX_P),
.TMDS_TX_N(HDMI_TX_N)
);

uivtc#
(
.H_ActiveSize(2560), 
.H_SyncStart(2560+30), 
.H_SyncEnd  (2560+30+50), 
.H_FrameSize(2560+30+50+80), 
.V_ActiveSize(1440), 

.V_SyncStart(1440+3), 
.V_SyncEnd (1440+3+5),
.V_FrameSize(1440+3+5+23)
)
uivtc_inst
(
.vtc_rstn_i(vid_rst),
.vtc_clk_i(vid_clk),
.vtc_vs_o(vid_vs),
.vtc_hs_o(vid_hs),
.vtc_de_o(vid_de)        
);

uitpg uitpg_inst        
(
.tpg_rstn_i(vid_rst),
.tpg_clk_i(vid_clk),
.tpg_vs_i(vid_vs),
.tpg_hs_i(vid_hs),
.tpg_de_i(vid_de),
.tpg_vs_o(),
.tpg_hs_o(),
.tpg_de_o(),        
.tpg_data_o({rgb_r,rgb_g,rgb_b})                
);

endmodule
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