DRR DMA实验疑惑

明天放假 · 发表于 2018-8-29 10:54:06

问题1：
DDR是内存，我的板子他的地址范围是
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF

接收发送缓存的基地址为
#define MEM_BASE_ADDR 0x01000000

#define TX_BUFFER_BASE (MEM_BASE_ADDR + 0x00100000)
#define RX_BUFFER_BASE (MEM_BASE_ADDR + 0x00300000)
#define RX_BUFFER_HIGH (MEM_BASE_ADDR + 0x004FFFFF)

所以我认为接收和发送数据也是存在DDR里面？

问题2:
DMA传输指令如下
Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) RxBufferPtr,MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);
Status = XAxiDma_SimpleTransfer(&AxiDma,(u32)TxBufferPtr,MAX_PKT_LEN,XAXIDMA_DMA_TO_DEVICE);

指令里面并没有涉及到DDR的目标地址，他存在哪里呢？
我顺着思路找到XAxiDma这个结构体
typedef struct XAxiDma {
u32 RegBase; /* Virtual base address of DMA engine */

int HasMm2S; /* Has transmit channel */
int HasS2Mm; /* Has receive channel */
int Initialized; /* Driver has been initialized */
int HasSg;

XAxiDma_BdRing TxBdRing;    /* BD container management for TX channel */
XAxiDma_BdRing RxBdRing[16]; /* BD container management for RX channel */
int TxNumChannels;
int RxNumChannels;
int MicroDmaMode;
int AddrWidth;    /**< Address Width */
} XAxiDma;

然后找到XAxiDma_BdRing 这个结构体
typedef struct {
u32 ChanBase; /**< physical base address*/

int IsRxChannel; /**< Is this a receive channel */
volatile int RunState; /**< Whether channel is running */
int HasStsCntrlStrm; /**< Whether has stscntrl stream */
int HasDRE;
int DataWidth;
int Addr_ext;
u32 MaxTransferLen;

UINTPTR FirstBdPhysAddr; /**< Physical address of 1st BD in list */
UINTPTR FirstBdAddr; /**< Virtual address of 1st BD in list */
UINTPTR LastBdAddr; /**< Virtual address of last BD in the list */
u32 Length; /**< Total size of ring in bytes */
UINTPTR Separation; /**< Number of bytes between the starting
      address of adjacent BDs */
XAxiDma_Bd *FreeHead; /**< First BD in the free group */
XAxiDma_Bd *PreHead; /**< First BD in the pre-work group */
XAxiDma_Bd *HwHead; /**< First BD in the work group */
XAxiDma_Bd *HwTail; /**< Last BD in the work group */
XAxiDma_Bd *PostHead; /**< First BD in the post-work group */
XAxiDma_Bd *BdaRestart; /**< BD to load when channel is started */
XAxiDma_Bd *CyclicBd; /**< Useful for Cyclic DMA operations */
int FreeCnt; /**< Number of allocatable BDs in free group */
int PreCnt; /**< Number of BDs in pre-work group */
int HwCnt; /**< Number of BDs in work group */
int PostCnt; /**< Number of BDs in post-work group */
int AllCnt; /**< Total Number of BDs for channel */
int RingIndex; /**< Ring Index */
int Cyclic; /**< Check for cyclic DMA Mode */
} XAxiDma_BdRing;

其中ChanBase就是物理的基地址。这个应该就是我们存在DDR里面的位置吧，是不是硬件已经帮他分配好了？而这个实验的目的就是ARM在DDR里面定义了一块内存区A，然后将A的数据通过DMA发送给DDR的另一块存储区B，最后将B的数据通过DMA发送到ARM在DDR里面定义的一块存储C？求大家指导一下！

uisrc · 发表于 2018-8-30 09:36:08

#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF
定义了 DDR 在ARM 32BIT 地址空间所在的地址范围，分别是低地址0x00100000 和高地址0x1FFFFFFF

#define MEM_BASE_ADDR             0x01000000

#define TX_BUFFER_BASE             (MEM_BASE_ADDR + 0x00100000)
#define RX_BUFFER_BASE             (MEM_BASE_ADDR + 0x00300000)
#define RX_BUFFER_HIGH             (MEM_BASE_ADDR + 0x004FFFFF)
定义的是我们程序里面用到的 DDR里面的存放空间的地址，这个必须在 DDR高低地址范围之间。