[第三季ZYNQ] CH02_AXI_DMA_PL_PS_ZYNQ 中的一些问题

本帖最后由 764332076 于 2017-5-17 10:48 编辑

首先感谢米联客的教程和视频，看了以后帮助很大！
这是关于[第三季ZYNQ] CH02_AXI_DMA_PL_PS_ZYNQ中的问题：
在这个工程中，我将axis_data_fifo_0的数据输入端由官方设计的
            if(S_AXIS_tready) begin
               S_AXIS_tdata <= S_AXIS_tdata + 1'b1;
               if(S_AXIS_tdata == 16'd1022) begin
                  S_AXIS_tlast <= 1'b1;
                  state <= 2;
               end

改为直接从外部获取数据，也就是插上了ADC板卡，其他部分不变，由于ADC是12位的精度，所以我只约束了32位S_AXIS_tdata的12位，所以顶层模块更改为：

`timescale 1 ps / 1 ps

module dma_system_wrapper
(
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
DC,
RES,
SCLK,
SDIN,
VBAT,
VDD,
      //ADC data signals
      ad_S_AXIS_tdata
      );
  output DC;
  inout [14:0]DDR_addr;
  inout [2:0]DDR_ba;
  inout DDR_cas_n;
  inout DDR_ck_n;
  inout DDR_ck_p;
  inout DDR_cke;
  inout DDR_cs_n;
  inout [3:0]DDR_dm;
  inout [31:0]DDR_dq;
  inout [3:0]DDR_dqs_n;
  inout [3:0]DDR_dqs_p;
  inout DDR_odt;
  inout DDR_ras_n;
  inout DDR_reset_n;
  inout DDR_we_n;
  inout FIXED_IO_ddr_vrn;
  inout FIXED_IO_ddr_vrp;
  inout [53:0]FIXED_IO_mio;
  inout FIXED_IO_ps_clk;
  inout FIXED_IO_ps_porb;
  inout FIXED_IO_ps_srstb;

  output RES;
  output SCLK;
  output SDIN;
  output VBAT;
  output VDD;

  input [15:0]ad_S_AXIS_tdata;

  wire DC;
  wire [14:0]DDR_addr;
  wire [2:0]DDR_ba;
  wire DDR_cas_n;
  wire DDR_ck_n;
  wire DDR_ck_p;
  wire DDR_cke;
  wire DDR_cs_n;
  wire [3:0]DDR_dm;
  wire [31:0]DDR_dq;
  wire [3:0]DDR_dqs_n;
  wire [3:0]DDR_dqs_p;
  wire DDR_odt;
  wire DDR_ras_n;
  wire DDR_reset_n;
  wire DDR_we_n;
  wire FCLK_CLK1;
  wire FIXED_IO_ddr_vrn;
  wire FIXED_IO_ddr_vrp;
  wire [53:0]FIXED_IO_mio;
  wire FIXED_IO_ps_clk;
  wire FIXED_IO_ps_porb;
  wire FIXED_IO_ps_srstb;
  wire RES;
  wire SCLK;
  wire SDIN;
  wire VBAT;
  wire VDD;

  wire [0:0]gpio_tri_i_0;
  wire [0:0]gpio_tri_io_0;
  wire [0:0]gpio_tri_o_0;
  wire [0:0]gpio_tri_t_0;
  wire [0:0]peripheral_aresetn;

  wire  m_axis_aclk;
  wire  s_axis_aclk;

  wire  [15:0]M_AXIS_tdata;
  wire  [1:0]M_AXIS_tkeep;
  wire  M_AXIS_tlast;
  wire  M_AXIS_tready;
  wire  M_AXIS_tvalid;

  assign M_AXIS_tready = 1'b1;

  reg [15:0]S_AXIS_tdata;
  wire  [1:0]S_AXIS_tkeep;
  reg S_AXIS_tlast;
  wire  S_AXIS_tready;
  reg S_AXIS_tvalid;
  reg [1:0]state;
  reg       [15:0]depth_cnt;

assign s_axis_aclk = FCLK_CLK1;
assign m_axis_aclk = FCLK_CLK1;
wire m_axis_aresetn;
wire s_axis_aresetn;
assign m_axis_aresetn = peripheral_aresetn;
assign s_axis_aresetn = peripheral_aresetn;
assign S_AXIS_tkeep = 2'b11;

always@(posedge FCLK_CLK1)
begin
   if(!peripheral_aresetn) begin
      S_AXIS_tvalid <= 1'b0;
      S_AXIS_tdata <= 32'd0;
      S_AXIS_tlast <= 1'b0;
               depth_cnt <= 1'b0;
      state <=0;
   end
   else begin
      case(state)
      0: begin
            if(gpio_tri_o_0&& S_AXIS_tready) begin
               S_AXIS_tvalid <= 1'b1;
               state <= 1;
            end
            else begin
               S_AXIS_tvalid <= 1'b0;
               state <= 0;
            end
         end
      1:begin
            if(S_AXIS_tready) begin
               S_AXIS_tdata <= ad_S_AXIS_tdata;
                                 depth_cnt       <= depth_cnt + 1'b1;
               if(depth_cnt == 16'd1022) begin
                  S_AXIS_tlast <= 1'b1;
                  state <= 2;
               end
               else begin
                  S_AXIS_tlast <= 1'b0;
                  state <= 1;
               end
            end
            else begin
               S_AXIS_tdata <= S_AXIS_tdata;
               state <= 1;
            end
         end
      2:begin
            if(!S_AXIS_tready) begin
               S_AXIS_tvalid <= 1'b1;
               S_AXIS_tlast <= 1'b1;
               S_AXIS_tdata <= S_AXIS_tdata;
               state <= 2;
            end
            else begin
               S_AXIS_tvalid <= 1'b0;
               S_AXIS_tlast <= 1'b0;
               S_AXIS_tdata <= 16'd0;
                              depth_cnt       <= 1'b0;
               state <= 0;
            end
         end
      default: state <=0;
      endcase
   end
end

  system system_i
   (.DC(DC),
      .DDR_addr(DDR_addr),
      .DDR_ba(DDR_ba),
      .DDR_cas_n(DDR_cas_n),
      .DDR_ck_n(DDR_ck_n),
      .DDR_ck_p(DDR_ck_p),
      .DDR_cke(DDR_cke),
      .DDR_cs_n(DDR_cs_n),
      .DDR_dm(DDR_dm),
      .DDR_dq(DDR_dq),
      .DDR_dqs_n(DDR_dqs_n),
      .DDR_dqs_p(DDR_dqs_p),
      .DDR_odt(DDR_odt),
      .DDR_ras_n(DDR_ras_n),
      .DDR_reset_n(DDR_reset_n),
      .DDR_we_n(DDR_we_n),
      .FCLK_CLK1(FCLK_CLK1),
      .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
      .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
      .FIXED_IO_mio(FIXED_IO_mio),
      .FIXED_IO_ps_clk(FIXED_IO_ps_clk),
      .FIXED_IO_ps_porb(FIXED_IO_ps_porb),
      .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
      .M_AXIS_tdata(M_AXIS_tdata),
      .M_AXIS_tkeep(M_AXIS_tkeep),
      .M_AXIS_tlast(M_AXIS_tlast),
      .M_AXIS_tready(M_AXIS_tready),
      .M_AXIS_tvalid(M_AXIS_tvalid),
      .m_axis_aresetn(m_axis_aresetn),
      .m_axis_aclk(m_axis_aclk),

      .S_AXIS_tdata({S_AXIS_tdata[15:0]}),
      .S_AXIS_tkeep(S_AXIS_tkeep),
      .S_AXIS_tlast(S_AXIS_tlast),
      .S_AXIS_tready(S_AXIS_tready),
      .S_AXIS_tvalid(S_AXIS_tvalid),
      .s_axis_aresetn(s_axis_aresetn),
      .s_axis_aclk(s_axis_aclk),

      .RES(RES),
      .SCLK(SCLK),
      .SDIN(SDIN),
      .VBAT(VBAT),
      .VDD(VDD),

      .gpio_rtl_tri_i(gpio_tri_i_0),
      .gpio_rtl_tri_o(gpio_tri_o_0),
      .gpio_rtl_tri_t(gpio_tri_t_0),

      .peripheral_aresetn(peripheral_aresetn)
      );
endmodule

SDK中的软件还是用的官方提供的版本，我将RxBufferPtr中的数据打印出来，代码如下

if(RX_ready)
            {
               RX_ready=0;
               Status = XAxiDma_SimpleTransfer(&AxiDma,(u32)RxBufferPtr,
                                    (u32)(MAX_PKT_LEN), XAXIDMA_DEVICE_TO_DMA);

               if (Status != XST_SUCCESS) {return XST_FAILURE;}
            }
            u32 rcv_buf[MAX_PKT_LEN];
            for(ii=0;ii<MAX_PKT_LEN;ii++)
            {
                     rcv_buf[ii] = RxBufferPtr[ii]&0xffff;
                     xil_printf("%u,",rcv_buf[ii]);
            }
采集的是1MHZ的方波，采样频率为50MHZ,最终观测到的数据如下：
65535,65471,65535,65535,61423,65535,65535,65535,65535,57343,65535,65535,65407,65535,65535,65535,65535,65469,65407,65535,57343,65534,65535,65407,65535,65535,65533,65397,65535,61439,65526,65535,65535,61439,65535,65279,65535,62463,65535,65535,65023,65535,65531,65535,65278,65471,65535,65471,65535,65535,65023,65407,65535,65471,57343,64511,65535,63487,65535,65535,65533,65535,65535,65535,65535,65535,65023,65535,65535,65531,65535,65535,65535,65535,65534,64511,64495,65535,32767,65023,65535,64959,65407,49151,65535,64511,65535,65535,65535,65535,64511,65535,65535,65535,32767,65535,65535,65535,65503,65535,65535,65535,65279,65535,32759,65535,65535,65535,65535,65535,65535,65535,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,6144,
可能是哪里出问题了呢？

zjkhurry · 发表于 2017-5-17 22:25:27

我也在做跟你相似的工作，但我把 FIFO的输入端改成连接外部数据的时候，SDK 运行代码就会报错退出，说是写入和读取失败，就是在
if(RX_ready)
            {
               RX_ready=0;
               Status = XAxiDma_SimpleTransfer(&AxiDma,(u32)RxBufferPtr,
                                    (u32)(MAX_PKT_LEN), XAXIDMA_DEVICE_TO_DMA);

               if (Status != XST_SUCCESS) {return XST_FAILURE;}
            }
这段代码之中，Error=0，在这段代码下面，Error 会立刻变成1，就算什么都没有执行，Error 也会变成1，这是什么原因呢？
如果你的问题有解决的办法，求解答

发表于 2017-5-19 10:04:13

zjkhurry 发表于 2017-5-17 22:25
我也在做跟你相似的工作，但我把 FIFO的输入端改成连接外部数据的时候，SDK 运行代码就会报错退出，说是写 ...

你的顶层模块是怎么修改的，我觉得问题可能出在这里

zjkhurry · 发表于 2017-5-20 12:32:11

764332076 发表于 2017-5-19 10:04
你的顶层模块是怎么修改的，我觉得问题可能出在这里

找到问题了，忘了在状态2里将计数器置0了

发表于 2017-5-20 21:15:52

zjkhurry 发表于 2017-5-20 12:32
找到问题了，忘了在状态2里将计数器置0了

采集数据正常吗？

zjkhurry · 发表于 2017-5-22 11:26:43

764332076 发表于 2017-5-20 21:15
采集数据正常吗？

我是使用 gpio 往里面传数据，还有一些 bug 还没调通

发表于 2017-5-23 16:19:04

zjkhurry 发表于 2017-5-22 11:26
我是使用 gpio 往里面传数据，还有一些 bug 还没调通

我也试过通过GPIO采集数据，不过这个有速度瓶颈，大概最多只能以2M速率采样，，

记忆中的我 · 发表于 2018-5-28 15:12:33

你好，我想问下，你是在CH02的block design加了ADC的IP核了吗？然后把ADC的IP核加了输出引脚，之后再在顶层模块里进行修改？

记忆中的我 · 发表于 2018-6-3 10:02:14

你好，你把assign s_axis_aclk = FCLK_CLK1; assign m_axis_aclk = FCLK_CLK1; 就没有出现[DRC 23-20] Rule violation (MDRV-1) Multiple Driver Nets - Net FCLK_CLK1_OBUF has multiple drivers: m00_axis_aclk_IBUF_inst/O, s_axis_aclk_IBUF_inst/O, system_i/processing_system7_0/inst/buffer_fclk_clk_1.FCLK_CLK_1_BUFG/O.的问题吗？

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