module led(
input CLK_i,
input RSTn_i,
output reg [7:0]LED_o
);
reg [31:0]C0;
always @(posedge CLK_i)
if(!RSTn_i)
begin
LED_o<=8'b0000_0001;
C0<=32'h0;
end
else
begin
if(C0==32'd50_000_000)
begin
C0<=32'h0;
if(LED_o==8'b1000_0000)
LED_o<=8'b0000_0001;
else LED_o<=LED_o<<1;
end
else begin C0<=C0+1'b1;LED_o<=LED_o;end
end
endmodule