AXI4总线 SLAVE部分的用户段谁来解释一下呢？

// ------------------------------------------
// -- Example code to access user logic memory region
// ------------------------------------------

generate
   if (USER_NUM_MEM >= 1)
      begin
      assign mem_select  = 1;
      assign mem_address = (axi_arv_arr_flag? axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:(axi_awv_awr_flag? axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:0));
      end
endgenerate

// implement Block RAM(s)
generate
   for(i=0; i<= USER_NUM_MEM-1; i=i+1)
      begin:BRAM_GEN
      wire mem_rden;
      wire mem_wren;

      assign mem_wren = axi_wready && S_AXI_WVALID ;

      assign mem_rden = axi_arv_arr_flag ; //& ~axi_rvalid

      for(mem_byte_index=0; mem_byte_index<= (C_S_AXI_DATA_WIDTH/8-1); mem_byte_index=mem_byte_index+1)
      begin:BYTE_BRAM_GEN
         wire [8-1:0] data_in ;
         wire [8-1:0] data_out;
         reg  [8-1:0] byte_ram [0 : 15];
         integer  j;

         //assigning 8 bit data
         assign data_in  = S_AXI_WDATA[(mem_byte_index*8+7) -: 8];
         assign data_out = byte_ram[mem_address];

         always @( posedge S_AXI_ACLK )
         begin
            if (mem_wren && S_AXI_WSTRB[mem_byte_index])
            begin
               byte_ram[mem_address] <= data_in;
            end
         end

         always @( posedge S_AXI_ACLK )
         begin
            if (mem_rden)
            begin
               mem_data_out[i][(mem_byte_index*8+7) -: 8] <= data_out;
            end
         end

      end
   end
endgenerate

車欠 · 发表于 2016-11-7 08:46:43

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