S02-CH20 利用EMIF进行PS与PL间数据交互

module system_top(

inout [14:0]DDR_addr,

inout [2:0]DDR_ba,

inout DDR_cas_n,

inout DDR_ck_n,

inout DDR_ck_p,

inout DDR_cke,

inout DDR_cs_n,

inout [3:0]DDR_dm,

inout [31:0]DDR_dq,

inout [3:0]DDR_dqs_n,

inout [3:0]DDR_dqs_p,

inout DDR_odt,

inout DDR_ras_n,

inout DDR_reset_n,

inout DDR_we_n,

inout FIXED_IO_ddr_vrn,

inout FIXED_IO_ddr_vrp,

inout [53:0]FIXED_IO_mio,

inout FIXED_IO_ps_clk,

inout FIXED_IO_ps_porb,

inout FIXED_IO_ps_srstb

);

wire clk_100m;

wire [31:0]mem_a;

wire [0 :0]mem_cen;

reg  [31:0]mem_dq_i;

wire [31:0]mem_dq_o;

wire [0 :0]mem_oen;

wire mem_wen;

//*************************************************************************

reg [31:0] data_reg1;

reg [31:0] data_reg2;

reg [31:0] data_reg3;

reg [31:0] data_reg4;

always @ (posedge clk_100m)

if(mem_wen==1'b0)begin

    case(mem_a)

   16'h0:begin

      data_reg1<=mem_dq_o;

   end

   16'h1:begin

          data_reg2<=mem_dq_o;

       end     

  16'h3:begin

          data_reg3<=mem_dq_o;

       end   

    16'h4:begin

          data_reg4<=mem_dq_o;

       end                                               

  default : begin         

   end  

endcase

end

always @ (posedge clk_100m)

if(mem_oen==1'b0)begin

    case(mem_a)

      16'h0:begin

         mem_dq_i<=data_reg1;

      end

      16'h1:begin

         mem_dq_i<=data_reg2;

      end     

      16'h3:begin

         mem_dq_i<=data_reg3;

      end   

      16'h4:begin

         mem_dq_i<=data_reg4;

      end                                                  

      default : begin         

      end     

  endcase

end

//*************************************************************************

wire [131:0] probe0;

ila_core ila_core_uut (

.clk(clk_100m), // input wire clk

.probe0(probe0) // input wire [99:0] probe0

);

assign probe0[31:0]=mem_a;

assign probe0[63:32]=mem_dq_o;

assign probe0[95:64]=mem_dq_i;

assign probe0[96]=mem_cen;

assign probe0[97]=mem_oen;

assign probe0[98]=mem_wen;

system system_i

       (.DDR_addr(DDR_addr),

        .DDR_ba(DDR_ba),

        .DDR_cas_n(DDR_cas_n),

        .DDR_ck_n(DDR_ck_n),

        .DDR_ck_p(DDR_ck_p),

        .DDR_cke(DDR_cke),

        .DDR_cs_n(DDR_cs_n),

        .DDR_dm(DDR_dm),

        .DDR_dq(DDR_dq),

        .DDR_dqs_n(DDR_dqs_n),

        .DDR_dqs_p(DDR_dqs_p),

        .DDR_odt(DDR_odt),

        .DDR_ras_n(DDR_ras_n),

        .DDR_reset_n(DDR_reset_n),

        .DDR_we_n(DDR_we_n),

        .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),

        .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),

        .FIXED_IO_mio(FIXED_IO_mio),

        .FIXED_IO_ps_clk(FIXED_IO_ps_clk),

        .FIXED_IO_ps_porb(FIXED_IO_ps_porb),

        .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),

        .clk_100m(clk_100m),

        .mem_a(mem_a),

        .mem_cen(mem_cen),

        .mem_dq_i(mem_dq_i),

        .mem_dq_o(mem_dq_o),

        .mem_oen(mem_oen),

        .mem_wen(mem_wen));

/*

 * main.c

 *

 *  Created on: 2019年5月21日

 *      Author: Administrator

 */

#include <stdio.h>

#include "sleep.h"

u32 data[4];

u32 i;

int main()

{

   for(i=0;i<4;i++)

   {

   Xil_Out32(XPAR_EMC_0_S_AXI_MEM0_BASEADDR+i*4,i);

   }

   sleep(1);

   for(i=0;i<4;i++)

   {

   data[i]=Xil_In32(XPAR_EMC_0_S_AXI_MEM0_BASEADDR+i*4);

   }

   for(i=0;i<4;i++)

   xil_printf("read %d = %d\n\r", i,data[i]);

    return 0;

}