S02-CH17 自定义IP AXI_PWM实验

always @( posedge S_AXI_ACLK )

begin

  if ( S_AXI_ARESETN == 1'b0 )

    begin

      slv_reg0 <= 0;

      slv_reg1 <= 0;

      slv_reg2 <= 0;

      slv_reg3 <= 0;

      slv_reg4 <= 0;

      slv_reg5 <= 0;

      slv_reg6 <= 0;

      slv_reg7 <= 0;

    end

  else begin

    if (slv_reg_wren)

      begin

        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )

          3'h0:

            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )

              if ( S_AXI_WSTRB[byte_index] == 1 ) begin

                // Respective byte enables are asserted as per write strobes

                // Slave register 0

                slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];

              end  

          3'h1:

            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )

              if ( S_AXI_WSTRB[byte_index] == 1 ) begin

                // Respective byte enables are asserted as per write strobes

                // Slave register 1

                slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];

              end  

          3'h2:

            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )

              if ( S_AXI_WSTRB[byte_index] == 1 ) begin

                // Respective byte enables are asserted as per write strobes

                // Slave register 2

                slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];

              end  

          3'h3:

            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )

              if ( S_AXI_WSTRB[byte_index] == 1 ) begin

                // Respective byte enables are asserted as per write strobes

                // Slave register 3

                slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];

              end  

          3'h4:

            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )

              if ( S_AXI_WSTRB[byte_index] == 1 ) begin

                // Respective byte enables are asserted as per write strobes

                // Slave register 4

                slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];

              end  

          3'h5:

            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )

              if ( S_AXI_WSTRB[byte_index] == 1 ) begin

                // Respective byte enables are asserted as per write strobes

                // Slave register 5

                slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];

              end  

          3'h6:

            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )

              if ( S_AXI_WSTRB[byte_index] == 1 ) begin

                // Respective byte enables are asserted as per write strobes

                // Slave register 6

                slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];

              end  

          3'h7:

            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )

              if ( S_AXI_WSTRB[byte_index] == 1 ) begin

                // Respective byte enables are asserted as per write strobes

                // Slave register 7

                slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];

              end  

          default : begin

                      slv_reg0 <= slv_reg0;

                      slv_reg1 <= slv_reg1;

                      slv_reg2 <= slv_reg2;

                      slv_reg3 <= slv_reg3;

                      slv_reg4 <= slv_reg4;

                      slv_reg5 <= slv_reg5;

                      slv_reg6 <= slv_reg6;

                      slv_reg7 <= slv_reg7;

                    end

        endcase

      end

  end

end     

module PWM(

input clk,

input rst_n,

input [31:0]fre_set,

input [31:0]wav_set,

output  PWM_o

);

reg [31:0]fre_cnt;

always @(posedge clk)begin

if(rst_n==1'b0)begin

fre_cnt <=32'd0;

end

else begin

if(fre_cnt<fre_set) begin

fre_cnt <= fre_cnt+1'b1;

end

else begin

fre_cnt<=32'd0;

end

end

end

assign PWM_o = (wav_set>fre_cnt);

endmodule