`timescale 1ns / 1ps module ft60x_top( // system control output USBSS_EN,//power enable // FIFO interface input CLK_i, inout [15:0] DATA_io, inout [1:0] BE_io, input RXF_N_i, // ACK_N input TXE_N_i, output reg OE_N_o, output WR_N_o, // REQ_N output SIWU_N_o, output reg RD_N_o, output WAKEUP_o, output [1:0] GPIO_o, // led output reg [3:0]LED, input [3:0]BTN ); assign USBSS_EN = 1'b1; assign WAKEUP_o = 1'b1; assign GPIO_o = 2'b00; assign SIWU_N_o = 1'b0; wire rstn; (*mark_debug = "true"*) wire RXF_N_i; // ACK_N (*mark_debug = "true"*) wire TXE_N_i; (*mark_debug = "true"*) reg OE_N_o; (*mark_debug = "true"*) reg WR_N_o; // REQ_N (*mark_debug = "true"*) reg RD_N_o; (*mark_debug = "true"*) (* KEEP = "TRUE" *)wire [15:0] rd_data; (*mark_debug = "true"*) (* KEEP = "TRUE" *)wire [15:0] wr_data; (*mark_debug = "true"*) (* KEEP = "TRUE" *)reg [31:0] rd_data_r; (*mark_debug = "true"*) wire [1 :0] BE_RD; (*mark_debug = "true"*) wire [1 :0] BE_WR; (*mark_debug = "true"*) reg [1:0] USB_S; wire data_rd_valid,data_wr_valid; assign data_rd_valid = (RD_N_o==1'b0)&&(RXF_N_i==1'b0); assign data_wr_valid = (WR_N_o==1'b0)&&(TXE_N_i==1'b0); //read or write flag assign rd_data = (USB_S==2'd1) ? DATA_io : 16'd0;//read data dir assign BE_RD = (USB_S==2'd1) ? BE_io : 2'd0; assign DATA_io = (USB_S==2'd2) ? wr_data : 16'bz;// write data dir assign BE_io = (USB_S==2'd2) ? BE_WR : 2'bz;// write data dir assign BE_WR = 4'b1111; assign wr_data = {8'hff,4'h0,BTN}; (*mark_debug = "true"*) (* KEEP = "TRUE" *) reg [15:0]rd_cnt; always @(posedge CLK_i)begin if(!rstn)begin rd_cnt <= 16'd0; end else if(data_rd_valid) begin rd_cnt <= rd_cnt + 1'b1; end else begin rd_cnt <= 16'd0; end end (*mark_debug = "true"*) (* KEEP = "TRUE" *)reg data_en; (*mark_debug = "true"*) (* KEEP = "TRUE" *)reg [1 :0] valid_r; reg [31:0] rd_data_r; always @(posedge CLK_i)begin if(!rstn)begin LED <= 4'b0000; end else if(data_en&&valid_r[1]) begin LED <= rd_data_r[3:0]; end end always @(posedge CLK_i)begin if(!rstn)begin rd_data_r <= 32'd0; valid_r <=2'b10; data_en <= 1'b0; end else if(data_rd_valid) begin data_en <= 1'b1; valid_r <= {valid_r[0],valid_r[1]}; rd_data_r <= {rd_data,rd_data_r[31:16]}; end else begin rd_data_r <= 32'd0; valid_r <=2'b10; data_en <= 1'b0; end end always @(posedge CLK_i)begin if(!rstn)begin USB_S <= 2'd0; OE_N_o <= 1'b1; RD_N_o <= 1'b1; WR_N_o <= 1'b1; end else begin case(USB_S) 0:begin OE_N_o <= 1'b1; RD_N_o <= 1'b1; WR_N_o <= 1'b1; if((!RXF_N_i)) begin USB_S <= 2'd1; OE_N_o <= 1'b0; end else if(!TXE_N_i)begin USB_S <= 2'd2; end end 1:begin RD_N_o <= 1'b0; if(RXF_N_i) begin USB_S <= 2'd0; RD_N_o <= 1'b1; OE_N_o <= 1'b1; end end 2:begin WR_N_o <= 1'b0; if(TXE_N_i) begin USB_S <= 2'd0; WR_N_o <= 1'b1; end end 3:begin USB_S <= 2'd0; end endcase end end Delay_rst #( .num(20'hffff0) ) Delay_rst_inst ( .clk_i(CLK_i), .rstn_i(1'b1), .rst_o(rstn) ); endmodule |