本帖最后由 FPGA课程 于 2024-10-21 18:43 编辑
软件版本:VIVADO2021.1
操作系统:WIN10 64bit
硬件平台:适用 XILINX A7/K7/Z7/ZU/KU 系列 FPGA
实验平台:米联客-MLK-H3-CZ08-7100开发板
板卡获取平台:https://milianke.tmall.com/
登录“米联客”FPGA社区 http://www.uisrc.com 视频课程、答疑解惑!
1 图像二值化开运算算法简介开运算就是先进行腐蚀然后进行膨胀,这样操作后可以使得原本连接在一起的区域,变成了不连通的区域。主 要针对细小的突起、细的连接线、图像中的弯口、孤立的小块或齿状物体的效果明显。 2 设计分析2.1Matlab代码分析 源代码如下:
- clear;clear all;clc;
- image_in = imread('geeker_fpga.jpg'); [row,col,n] = size(image_in);
- image_gray = rgb2gray(image_in);
- image_binary=zeros(row,col); for i=1:row
- for j=1:col
- if image_gray(i,j) > 92%阈值处理
- image_binary(i,j)=255; else
- image_binary(i,j)=0; end
- end end
- %开运算先腐蚀后膨胀
- image_erode_0=zeros(row,col); for i = 2:1:row-1
- for j = 2:1:col-1
- image_erode_0(i,j) =...
- image_binary(i-1,j-1)&image_binary(i-1,j)&image_binary(i-1,j+1)&... image_binary(i,j-1) &image_binary(i,j) &image_binary(i,j+1) &... image_binary(i+1,j-1)&image_binary(i+1,j)&image_binary(i+1,j+1);
- end end
- image_erode_1=zeros(row,col); for i = 2:1:row-1
- for j = 2:1:col-1
- image_erode_1(i,j) =...
- image_erode_0(i-1,j-1)&image_erode_0(i-1,j)&image_erode_0(i-1,j+1)&... image_erode_0(i,j-1) &image_erode_0(i,j) &image_erode_0(i,j+1) &... image_erode_0(i+1,j-1)&image_erode_0(i+1,j)&image_erode_0(i+1,j+1);
- end end
- image_erode_2=zeros(row,col); for i = 2:1:row-1
- for j = 2:1:col-1
- image_erode_2(i,j) =...
- image_erode_1(i-1,j-1)&image_erode_ 1(i-1,j)&image_erode_ 1(i-1,j+1)&... image_erode_1(i,j-1) &image_erode_ 1(i,j) &image_erode_ 1(i,j+1) &... image_erode_1(i+1,j-1)&image_erode_ 1(i+1,j)&image_erode_ 1(i+1,j+1);
- end end
- image_dilate_0=zeros(row,col); for i = 2:1:row-1
- for j = 2:1:col-1
- image_dilate_0(i,j) =...
- image_erode_2(i-1,j-1)|image_erode_2(i-1,j)|image_erode_2(i-1,j+1)|... image_erode_2(i,j-1) |image_erode_2(i,j) |image_erode_2(i,j+1) |... image_erode_2(i+1,j-1)|image_erode_2(i+1,j)|image_erode_2(i+1,j+1);
- end end
- image_dilate_ 1=zeros(row,col); for i = 2:1:row-1
- for j = 2:1:col-1
- image_dilate_ 1(i,j) =...
- image_dilate_0(i-1,j-1)|image_dilate_0(i-1,j)|image_dilate_0(i-1,j+1)|... image_dilate_0(i,j-1) |image_dilate_0(i,j) |image_dilate_0(i,j+1) |... image_dilate_0(i+1,j-1)|image_dilate_0(i+1,j)|image_dilate_0(i+1,j+1);
- end end
- image_dilate_2=zeros(row,col); for i = 2:1:row-1
- for j = 2:1:col-1
- image_dilate_2(i,j) =...
- image_dilate_ 1(i-1,j-1)|image_dilate_ 1(i-1,j)|image_dilate_ 1(i-1,j+1)|... image_dilate_ 1(i,j-1) |image_dilate_ 1(i,j) |image_dilate_ 1(i,j+1) |...
- image_dilate_ 1(i+1,j-1)|image_dilate_ 1(i+1,j)|image_dilate_ 1(i+1,j+1); end
- end
- subplot(331);
- imshow(image_gray); title('the image gray image'); subplot(332);
- imshow(image_binary); title('the image binary image');
- subplot(334);
- imshow(image_erode_0); title('the image erode 0 image'); subplot(335);
- imshow(image_erode_ 1); title('the image erode 1 image'); subplot(336);
- imshow(image_erode_2); title('the image erode 2 image');
- subplot(337);
- imshow(image_dilate_0); title('the image dilate 0 image'); subplot(338);
- imshow(image_dilate_ 1); title('the image dilate 1 image'); subplot(339);
- imshow(image_dilate_2); title('the image dilate 2 image');
复制代码
2.2Verilog代码分析 - image_erode_filtering u_image_erode_filtering (
- .i_clk (i_clk ),
- .i_rst_n (i_rst_n ),
- .i_hsyn (i_hsyn ),
- .i_vsyn (i_vsyn ),
- .i_en (i_en ),
- .i_binary (i_binary ),
- .o_hs (erode_hsyn ),
- .o_vs (erode_vsyn ),
- .o_en (erode_de ),
- .o_binary (erode_data )
- );
- image_dilate_filtering u_image_dilate_filtering (
- .i_clk (i_clk ),
- .i_rst_n (i_rst_n ),
- .i_hsyn (erode_hsyn ),
- .i_vsyn (erode_vsyn ),
- .i_en (erode_de ),
- .i_binary (erode_data ),
- .o_hs (dilate_hsyn ),
- .o_vs (dilate_vsyn ),
- .o_en (dilate_de ),
- .o_binary (dilate_data )
- );
复制代码
2.3 工程结构分析
我们将图像算法的模块做成 IP 后,在vivado 中进行工程的搭建,工程结构如图所示:
3 仿真及结果3.1Matlab实验结果
3.2Modelsim实验结果
4 搭建 Vitis-sdk 工程创建 soc_base sdk platform 和 APP 工程的过程不再重复,可以阅读 3-3-01_sdk_base_app。以下给出创建好 soc_base sdk platform 的截图和对应工程 APP 的截图。 4.1 创建 SDKPlatform工程
4.2SDKAPP工程
5 硬件连接硬件连接如图所示:
6 上板实验结果实验结果如图所示:
|