(AXI4)S02- CH01 基于FDMA内存读写测试

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:CZ123 MSXBO www.osrc.cn

// Engineer: tjy

// Create Date: 2019/04/02 12:39:25

// Design Name:

// Module Name: fdma_top

// Project Name: AXI_FDMA

// Target Devices:

// Tool Versions: VIVADO

// Description: test DDR

// Dependencies:

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////

module fdma_top(

output [13:0]DDR3_addr,

output [2:0]DDR3_ba,

output DDR3_cas_n,

output [0:0]DDR3_ck_n,

output [0:0]DDR3_ck_p,

output [0:0]DDR3_cke,

output [0:0]DDR3_cs_n,

output [1:0]DDR3_dm,

inout [15:0]DDR3_dq,

inout [1:0]DDR3_dqs_n,

inout [1:0]DDR3_dqs_p,

output [0:0]DDR3_odt,

output DDR3_ras_n,

output DDR3_reset_n,

output DDR3_we_n,

input sys_clk_i

);

  wire [0:0]ui_rstn;

  wire ui_clk;

  //-----------------fmda signals--------------------------------------

  wire [31:0] pkg_wr_addr;

 (*mark_debug = "true"*)  wire  [31:0] pkg_wr_data;

 (*mark_debug = "true"*) (* KEEP = "TRUE" *)  reg         pkg_wr_areq;

 (*mark_debug = "true"*)  wire        pkg_wr_en;

 (*mark_debug = "true"*)  wire        pkg_wr_last;

  wire [31:0] pkg_wr_size;

  wire [31:0] pkg_rd_addr;

 (*mark_debug = "true"*)  wire  [31:0] pkg_rd_data;

 (*mark_debug = "true"*) (* KEEP = "TRUE" *) reg         pkg_rd_areq;

 (*mark_debug = "true"*)  wire        pkg_rd_en;

 (*mark_debug = "true"*)  wire        pkg_rd_last;

  wire [31:0] pkg_rd_size;

 //---------------------------------------------------------------------

  reg [31:0]pkg_wr_cnt;

 (*mark_debug = "true"*) (* KEEP = "TRUE" *) reg [31:0]pkg_rd_cnt;

 (*mark_debug = "true"*) (* KEEP = "TRUE" *) reg [1:0] T_S;

  reg [31:0] pkg_addr;

  parameter WRITE1 = 0;

  parameter WRITE2 = 1;

  parameter READ1  = 2;

  parameter READ2  = 3;

  //-----------------  

  assign pkg_wr_size = 1024;

  assign pkg_rd_size = 1024;

  assign pkg_wr_data = pkg_wr_cnt;

  (*mark_debug = "true"*) wire test_error;

  assign test_error = (pkg_rd_en && (pkg_rd_cnt != pkg_rd_data));

  assign pkg_wr_addr = pkg_addr;

  assign pkg_rd_addr = pkg_addr;

  always @(posedge ui_clk)

  begin

    if(!ui_rstn)begin

        T_S <=0;

        pkg_wr_areq <= 1'b0;

        pkg_rd_areq <= 1'b0;         

        pkg_wr_cnt<=0;

        pkg_rd_cnt<=0;

        pkg_addr<=0;       

    end

    else begin

        case(T_S)

        WRITE1:begin

            if(pkg_addr>=32'd268435455) pkg_addr<=0;

            pkg_wr_areq  <= 1'b1;

            T_S <= WRITE2;

        end

        WRITE2:begin

            pkg_wr_areq  <= 1'b0;

            if(pkg_wr_last) begin

                 T_S <= READ1;

                 pkg_wr_cnt <= 32'd0;

            end

            else if(pkg_wr_en) begin

                pkg_wr_cnt <= pkg_wr_cnt + 1'b1;

            end

        end

        READ1:begin

            pkg_rd_areq <= 1'b1;

            T_S <= READ2;   

        end   

        READ2:begin

            pkg_rd_areq <= 1'b0;

            if(pkg_rd_last) begin

                T_S <= WRITE1;  

                pkg_addr <= pkg_addr + 4096;

                pkg_rd_cnt <= 32'd0;

            end

            else if(pkg_rd_en) begin

                pkg_rd_cnt <= pkg_rd_cnt + 1'b1;

            end

        end             

        endcase

    end

  end

  system system_i

       (.DDR3_addr(DDR3_addr),

        .DDR3_ba(DDR3_ba),

        .DDR3_cas_n(DDR3_cas_n),

        .DDR3_ck_n(DDR3_ck_n),

        .DDR3_ck_p(DDR3_ck_p),

        .DDR3_cke(DDR3_cke),

        .DDR3_cs_n(DDR3_cs_n),

        .DDR3_dm(DDR3_dm),

        .DDR3_dq(DDR3_dq),

        .DDR3_dqs_n(DDR3_dqs_n),

        .DDR3_dqs_p(DDR3_dqs_p),

        .DDR3_odt(DDR3_odt),

        .DDR3_ras_n(DDR3_ras_n),

        .DDR3_reset_n(DDR3_reset_n),

        .DDR3_we_n(DDR3_we_n),

        .pkg_wr_addr(pkg_wr_addr),

        .pkg_wr_data(pkg_wr_data),

        .pkg_wr_areq(pkg_wr_areq),

        .pkg_wr_en  (pkg_wr_en),

        .pkg_wr_last(pkg_wr_last),

        .pkg_wr_size(pkg_wr_size),

        .pkg_rd_addr(pkg_rd_addr),

        .pkg_rd_data(pkg_rd_data),

        .pkg_rd_areq(pkg_rd_areq),  

        .pkg_rd_en  (pkg_rd_en),   

        .pkg_rd_last(pkg_rd_last),

        .pkg_rd_size(pkg_rd_size),

        .ui_clk(ui_clk),

        .fdma_rstn(ui_rstn),        

        .sys_clk_i(sys_clk_i)       

        );

endmodule

assign test_error = (pkg_rd_en && (pkg_rd_cnt != pkg_rd_data));