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【ZYNQ-7000开发之四】在PS端使用AXI DMA传输的步骤

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RZJM 发表于 2015-12-16 02:32:58 | 显示全部楼层 |阅读模式 打印 上一主题 下一主题
 
本帖最后由 RZJM 于 2015-12-16 12:30 编辑

本篇文章简要总结下AXI DMA在ZYNQ PS端的初始化方法。本文摘抄自xilinx SDK的API文档,更加详细的内容请参考官方文档,这里只提取了关键部分。

  AXI DMA有两种模式,Direct Register Mode(不支持Scatter Gather)和   Scatter Gather Mode。
  AXI DMA用于AXI4 memory mapped和AXI4-Stream之间的转换
  Scatter Gather Mode性能更好,更消耗逻辑资源,使用更复杂一些。
  Direct Register Mode则相反。
  • AXI DMA更加详细的介绍请参考:pg021_axi_dma.pdf

    使用AXI DMA传输的步骤:
    非Scatter Gather mode
    To use the Simple mode DMA engine for transfers, the following setup is required:


    • DMA Initialization using XAxiDma_CfgInitialize() function. This step initializes a driver instance for the given DMA engine and resets the engine.

    • Enable interrupts if chosen to use interrupt mode. The application is responsible for setting up the interrupt system, which includes providing and connecting interrupt handlers and call back functions, before enabling the interrupts.

    • Set the buffer address and length field in respective channels to start the DMA transfer



    使用Scatter Gather mode
    To use the SG mode DMA engine for transfers, the following setup are required:
    • DMA Initialization using XAxiDma_CfgInitialize() function. This step initializes a driver instance for the given DMA engine and resets the engine.

    • BD Ring creation. A BD ring is needed per DMA channel and can be built by calling XAxiDma_BdRingCreate().

    • Enable interrupts if chose to use interrupt mode. The application is responsible for setting up the interrupt system, which includes providing and connecting interrupt handlers and call back functions, before enabling the interrupts.

    • Start a DMA transfer: Call XAxiDma_BdRingStart() to start a transfer for the first time or after a reset, and XAxiDma_BdRingToHw() if the channel is already started. Calling XAxiDma_BdRingToHw() when a DMA channel is not running will not put the BDs to the hardware, and the BDs will be processed later when the DMA channel is started through XAxiDma_BdRingStart().



    How to start DMA transactions
    The user application uses XAxiDma_BdRingToHw() to submit BDs to the  hardware to start DMA transfers.
    For both channels, if the DMA engine is currently stopped (using  XAxiDma_Pause()), the newly added BDs will be accepted but not  processed until the DMA engine is started, using XAxiDma_BdRingStart(),  or resumed, using XAxiDma_Resume().

    Post-Processing 这个还不是很了解
    Software Post-Processing on completed DMA transactions
    If the interrupt system has been set up and the interrupts are enabled,  a DMA channels notifies the software about the completion of a transfer  through interrupts. Otherwise, the user application can poll for  completions of the BDs, using XAxiDma_BdRingFromHw() or  XAxiDma_BdHwCompleted().
    • Once BDs are finished by a channel, the application first needs to fetch them from the channel using XAxiDma_BdRingFromHw().

    • On the TX side, the application now could free the data buffers attached to those BDs as the data in the buffers has been transmitted.

    • On the RX side, the application now could use the received data in the buffers attached to those BDs.

    • For both channels, completed BDs need to be put back to the Free group using XAxiDma_BdRingFree(), so they can be used for future transactions.

    • On the RX side, it is the application's responsibility to have BDs ready to receive data at any time. Otherwise, the RX channel refuses to accept any data if it has no RX BDs.



 

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贾文洋 发表于 2015-12-17 21:12:18 | 显示全部楼层
 
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mine_2000 发表于 2015-12-23 19:45:10 | 显示全部楼层
 
待传输的数据在DDR中时,需使用Xil_DCacheFlushRange函数更新后再发送。

请教SDK里面是否可指定部分内存空间不使用CACHE?
 
RZJM 发表于 2015-12-23 21:16:35 | 显示全部楼层
 
mine_2000 发表于 2015-12-23 19:45
待传输的数据在DDR中时,需使用Xil_DCacheFlushRange函数更新后再发送。

请教SDK里面是否可指定部分内存 ...

恩。我也在研究学习,我目前不确定。还没有实际测试过。为什么指定部分内存?这样速度不是很慢吗?
 
 楼主| RZJM 发表于 2015-12-23 21:30:27 | 显示全部楼层
 
mine_2000 发表于 2015-12-23 19:45
待传输的数据在DDR中时,需使用Xil_DCacheFlushRange函数更新后再发送。

请教SDK里面是否可指定部分内存 ...

关于Cache文章http://www.360doc.com/content/11/1023/18/1317564_158491732.shtml

 
 楼主| mine_2000 发表于 2015-12-24 19:06:54 | 显示全部楼层
 
RZJM 发表于 2015-12-23 21:16
恩。我也在研究学习,我目前不确定。还没有实际测试过。为什么指定部分内存?这样速度不是很慢吗?

用DDR做VGA显存空间,这部分空间不希望Cacse,不然更新显存数据后还得刷新,反而降低刷屏速度
 
RZJM 发表于 2015-12-26 00:27:35 | 显示全部楼层
 
mine_2000 发表于 2015-12-24 19:06
用DDR做VGA显存空间,这部分空间不希望Cacse,不然更新显存数据后还得刷新,反而降低刷屏速度

据我目前了解如果使用ACP,可以不用更新cache。ACP可以保证缓存一致性。
 
 楼主| mine_2000 发表于 2015-12-26 08:22:07 | 显示全部楼层
 
RZJM 发表于 2015-12-26 00:27
据我目前了解如果使用ACP,可以不用更新cache。ACP可以保证缓存一致性。

ACP是啥,我用IP核中VDMA模块,加上自己做的数据流转VGA信号。
 
RZJM 发表于 2015-12-26 11:37:36 | 显示全部楼层
 
mine_2000 发表于 2015-12-26 08:22
ACP是啥,我用IP核中VDMA模块,加上自己做的数据流转VGA信号。

个人理解,如果使用的AXI_HP接口和PS的DDR通信,应该需要刷新cache。如果使用AXI_ACP接口和PS通信不用刷新cache,但是这种方式可能不适合数据量特别大的通信,会影响到PS的性能。不过我认为你说的那个刷新应该不是系统的瓶颈吧,瓶颈还是数据在DDR和PL之间的拷贝延时。不知道理解的多不对......
 
 楼主| mine_2000 发表于 2015-12-26 14:13:16 | 显示全部楼层
 
我换成ACP试下,回头报告测试情况
 
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