spartan6 ddr3的IP核无法生成

从店里买的sp6 xc6slx45t这块板子，用淘宝店里上面的百度云盘链接下载ddr3 mcb读写源代码，发现在ise中无法生成ip核。生成过程中没有报错，但是进度条到70%左右就自动停止了。同时还发现源代码可能缺少一些文件。请问怎么解决？
ise版本为14.6

这种问题？？？代码不全？

贾文洋 发表于 2015-12-30 20:49
这种问题？？？代码不全？

不清楚啊，当初汤工给我的代码就是这些

今天下载了everything，从Xilinx文件夹里面找到了缺失的文件，把缺失的文件补齐之后，先进行综合，没有报错，但是发现了一堆warning，比如50MHz的时钟没有和instance连接上，如下图所示：
然后尝试生成ip核，还是遇到和昨天一样的问题，无法生成ip核，生成日志如下：
Welcome to Xilinx CORE Generator.
Help system initialized.
The IP Catalog has been reloaded.
Opening project file C:\Users\Administrator\Desktop\SP6_MARS_G6\DDR3_Test\ipcore_dir\coregen.cgp.
Closed project file.
Wrote CGP file for project 'ddr3'.
Customize and Generate
INFO:sim:172 - Generating IP...
Applying current project options...
Finished applying current project options.
Customizing IP...
Finished Customizing.
Resolving generic values...
Finished resolving generic values.
INFO:sim:993 - The selected IP does not support an ASY schematic symbol.
INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating metadata file...
Generating ISE project...
XCO file found: mig_39_2.xco
XMDF file found: mig_39_2_xmdf.tcl
Adding C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_39_2/user_design/rtl/infrastructure.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_
   39_2/user_design/rtl/infrastructure.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_39_2/user_design/rtl/mcb_controller/iodrp_controller.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_
   39_2/user_design/rtl/mcb_controller/iodrp_controller.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_39_2/user_design/rtl/mcb_controller/iodrp_mcb_controller.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_
   39_2/user_design/rtl/mcb_controller/iodrp_mcb_controller.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_39_2/user_design/rtl/mcb_controller/mcb_raw_wrapper.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_
   39_2/user_design/rtl/mcb_controller/mcb_raw_wrapper.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_39_2/user_design/rtl/mcb_controller/mcb_soft_calibration.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_
   39_2/user_design/rtl/mcb_controller/mcb_soft_calibration.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_39_2/user_design/rtl/mcb_controller/mcb_soft_calibration_top.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_
   39_2/user_design/rtl/mcb_controller/mcb_soft_calibration_top.v" into library
   work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_39_2/user_design/rtl/mcb_controller/mcb_ui_top.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_
   39_2/user_design/rtl/mcb_controller/mcb_ui_top.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_39_2/user_design/rtl/memc_wrapper.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_
   39_2/user_design/rtl/memc_wrapper.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_39_2/user_design/rtl/mig_39_2.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_
   39_2/user_design/rtl/mig_39_2.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding C:/Users/Administrator/Desktop/SP6_MARS_G6/DDR3_Test/ipcore_dir/tmp/_cg/mig_39_2/user_design/par/mig_39_2.ucf -view all -origin_type created
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
Top level has been set to "/mig_39_2"
Generating README file...
Generating FLIST file...
INFO:sim:948 - Finished FLIST file generation.
Launching README viewer...
Moving files to output directory...
Finished moving files to output directory
Saved CGP file for project 'ddr3'.