bitstream generation failed

ERROR: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 4 out of 138 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: PWM[7], PWM[6], PWM[5], PWM[4].
ERROR: [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 4 out of 138 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: PWM[7], PWM[6], PWM[5], PWM[4].
INFO: [Vivado 12-3199] DRC finished with 2 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
INFO: [Common 17-83] Releasing license: Implementation
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.

BD 设计的程序自动产生的文件， PWM信号中PWM[7], PWM[6], PWM[5], PWM[4].没有使用，但是引出到了顶层模块，你可以修改顶层的代码，不让PWM[7], PWM[6], PWM[5], PWM[4].引出去