您好。
1.我将顶层文件中,HDMI_FPGA_ML_0 模块注释了,也将hdmi_data_gen中的RGB改为了顶层文件中的输出,但RUN Behavioral Simulation 仍报上面的那两个错误。请指导该如何HDMI接口注释,引出RGB。
2.我想生成MCS和BIN,发现只能用SPI x1生成。在约束文件中,加了4.7中优化管脚约束的几行后,才ok了。这正确吧,百度查了,但对于约束中增加的几行的具体含义还不是很清楚。请问有vivado 2017.4及约束、仿真等相关必须了解的工具知识等的中文书籍推荐吗?谢谢。
约束中的六行代码是:
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design]
为了仿真,修改的顶层文件是:
module HDMI_display_Demon(
input clk_50M,
input KEY,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE,
/* output HDMI_CLK_P,
output HDMI_CLK_N,
output HDMI_D2_P,
output HDMI_D2_N,
output HDMI_D1_P,
output HDMI_D1_N,
output HDMI_D0_P,
output HDMI_D0_N,*/
output [3:0] LED
);
wire pixclk;
//wire[7:0] R,G,B;
//wire HS,VS,DE;
hdmi_data_gen u_hdmi_data_gen
(
.pix_clk (pixclk),
.turn_mode (KEY),
.VGA_R (VGA_R),
.VGA_G (VGA_G),
.VGA_B (VGA_B),
.VGA_HS (VGA_HS),
.VGA_VS (VGA_VS),
.VGA_DE (VGA_DE),
/* .VGA_R (R),
.VGA_G (G),
.VGA_B (B),
.VGA_HS (HS),
.VGA_VS (VS),
.VGA_DE (DE),*/
.mode (LED)
);
wire serclk;
wire lock;
wire[23:0] RGB;
//assign RGB={R,G,B};
/*
HDMI_FPGA_ML_0 u_HDMI
(
.PXLCLK_I (pixclk),
.PXLCLK_5X_I (serclk),
.LOCKED_I (lock),
.RST_N (1'b1),
.VGA_HS (HS),
.VGA_VS (VS),
.VGA_DE (DE),
.VGA_RGB (RGB),
.HDMI_CLK_P (HDMI_CLK_P),
.HDMI_CLK_N (HDMI_CLK_N),
.HDMI_D2_P (HDMI_D2_P),
.HDMI_D2_N (HDMI_D2_N),
.HDMI_D1_P (HDMI_D1_P),
.HDMI_D1_N (HDMI_D1_N),
.HDMI_D0_P (HDMI_D0_P),
.HDMI_D0_N (HDMI_D0_N)
); */
hdmi_clk u_clk
(
.clk_in1 (clk_50M),
.resetn (1'b1),
.clk_out1 (pixclk),
.clk_out2 (serclk),
.locked (lock)
);
endmodule
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