verilog HDL代码问题
如下代码,在同一个always块中,两个if判断条件同时对一个reg变量进行赋值,是否会潜在逻辑冲突?还是存在先后顺序(优先级)?always @(posedge video_clk)
begin
if(video_rst)
begin
fifo_ren <= 1'b0;
sof_err_to_sof <= 1'b0;
end
else
begin
if(sof_err && !sof && !sof_err_to_sof)
fifo_ren <= 1'b1;
else if(sof_err && sof)
begin
fifo_ren <= 1'b0;
sof_err_to_sof <= 1'b1;
end
if(locked && de_rising_r1)
begin
fifo_ren <= 1'b1;
sof_err_to_sof <= 1'b0;
end
else if(eol)
fifo_ren <= 1'b0;
end
end
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