参考的一个三段式状态机,感觉有问题,大家来看看
module detect_3(
input clk_i,
input rst_n_i,
output out_o
);
reg out_r;
//状态声明和状态编码
reg Current_state;
reg Next_state;
parameter S0=2'b00;
parameter S1=2'b01;
parameter S2=2'b10;
parameter S3=2'b11;
//时序逻辑:描述状态转换
always@(posedge clk_i)
begin
if(!rst_n_i)
#2 Current_state<=0;
else
#2 Current_state<=Next_state;
end
//组合逻辑:描述下一状态
always@(Current_state)
begin
case(Current_state)
S0:
#0.5 Next_state = S1;
S1:
#0.5 Next_state = S2;
S2:
#0.5 Next_state = S3;
S3:
begin
Next_state = Next_state;
end
endcase
end
//输出逻辑:让输出out,经过寄存器out_r锁存后输出,消除毛刺
always@(posedge clk_i)
begin
if(!rst_n_i)
out_r<=1'b0;
else
begin
out_r<=1'b0;
case(Current_state)
S0,S2:
#2 out_r<=1'b0;
S1,S3:
#2 out_r<=1'b1;
endcase
end
end
assign out_o=out_r;
仿真结果
逻辑性,没问题,case要完整
母子平安 发表于 2016-6-21 15:01
逻辑性,没问题,case要完整
没有不可知的case
这个部分完善了,always(*)
module detect_3( input clk_i, input rst_n_i, output out_o ); reg out_r; //状态声明和状态编码 reg Current_state; reg Next_state; parameter S0=2'b00; parameter S1=2'b01; parameter S2=2'b10; parameter S3=2'b11; //时序逻辑:描述状态转换 always@(posedge clk_i) begin if(!rst_n_i)#2 Current_state<=0; else#2 Current_state<=Next_state; end //组合逻辑:描述下一状态 always@(*) begin case(Current_state) S0: #0.5 Next_state = S1; S1: #0.5 Next_state = S2; S2: #0.5 Next_state = S3; S3: begin Next_state = Next_state; end default : Next_state = S0; endcase end //输出逻辑:让输出out,经过寄存器out_r锁存后输出,消除毛刺 always@(posedge clk_i) begin if(!rst_n_i) out_r<=1'b0; else begin case(Current_state) S0,S2: #2 out_r<=1'b0; S1,S3: #2 out_r<=1'b1; default : out_r<=out_r; endcase end end assign out_o=out_r;
always@(*) 和 always@(Current_state) 在这个代码里好像区别不大
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